src/mainboard/google/nyan_big/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <bootblock_common.h>
  18 #include <console/console.h>
  19 #include <device/i2c.h>
  20 #include <gpio.h>
  21 #include <soc/addressmap.h>
  22 #include <soc/clk_rst.h>
  23 #include <soc/clock.h>
  24 #include <soc/nvidia/tegra/i2c.h>
  25 #include <soc/pinmux.h>
  26 #include <soc/spi.h>    /* FIXME: move back to soc code? */
  27
  28 #include "pmic.h"
  29
  30 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
  31
  32 static void set_clock_sources(void)
  33 {
  34         /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
  35         write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
  36
  37         clock_configure_source(mselect, PLLP, 102000);
  38
  39         /* The PMIC is on I2C5 and can run at 400 KHz. */
  40         clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
  41
  42         /* TODO: We should be able to set this to 50MHz, but that did not seem
  43          * reliable. */
  44         clock_configure_source(sbc4, PLLP, 33333);
  45 }
  46
  47 void bootblock_mainboard_init(void)
  48 {
  49         set_clock_sources();
  50
  51         clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
  52                                  CLK_H_I2C5 | CLK_H_APBDMA,
  53                                  0, CLK_V_MSELECT, 0, 0);
  54
  55         // Board ID GPIOs, bits 0-3.
  56         gpio_input(GPIO(Q3));
  57         gpio_input(GPIO(T1));
  58         gpio_input(GPIO(X1));
  59         gpio_input(GPIO(X4));
  60
  61         // I2C5 (PMU) clock.
  62         pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
  63                           PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
  64         // I2C5 (PMU) data.
  65         pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
  66                           PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
  67         i2c_init(4);
  68         pmic_init(4);
  69
  70         /* SPI4 data out (MOSI) */
  71         pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
  72                           PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
  73                           PINMUX_PULL_UP);
  74         /* SPI4 data in (MISO) */
  75         pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
  76                           PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
  77                           PINMUX_PULL_UP);
  78         /* SPI4 clock */
  79         pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
  80                           PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
  81         /* SPI4 chip select 0 */
  82         pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
  83                           PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
  84
  85         tegra_spi_init(4);
  86 }