src/mainboard/google/nyan/devicetree.cb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright 2014 Google Inc.
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; version 2 of the License.
   9 ##
  10 ## This program is distributed in the hope that it will be useful,
  11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ## GNU General Public License for more details.
  14 ##
  15
  16 chip soc/nvidia/tegra124
  17         device cpu_cluster 0 on end
  18 # N.B. We ae not using the device tree in an effective way.
  19 # We need to change this in future such that the on-soc
  20 # devices are 'chips', which will allow us to go at them
  21 # in parallel. This is even easier on the ARM SOCs since there
  22 # are no single-access resources such as the infamous
  23 # cf8/cfc registers found on PCs.
  24         register "display_controller" = "TEGRA_ARM_DISPLAYA"
  25         register "xres" = "1366"
  26         register "yres" = "768"
  27
  28         # bits per pixel and color depth
  29         register "framebuffer_bits_per_pixel" = "16"
  30         register "color_depth" = "6"
  31         # "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
  32
  33         register "panel_bits_per_pixel" = "18"
  34
  35         register "cache_policy" = "DCACHE_WRITETHROUGH"
  36
  37         # With some help from the mainbaord designer
  38         register "backlight_en_gpio" = "GPIO(H2)"
  39         register "lvds_shutdown_gpio" = "0"
  40         register "backlight_vdd_gpio" = "GPIO(P2)"
  41         register "panel_vdd_gpio" = "0"
  42         register "pwm" = "1"
  43
  44         # various panel delay time
  45         register "vdd_delay_ms" = "200"
  46         register "pwm_to_bl_delay_ms" = "10"
  47         register "vdd_to_hpd_delay_ms" = "200"
  48         register "hpd_unplug_min_us" = "2000"
  49         register "hpd_plug_min_us" = "250"
  50         register "hpd_irq_min_us" = "250"
  51
  52 # How to compute these: xrandr --verbose will give you this:
  53 #Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
  54 #               2560 2608 2640 2720 hborder 0
  55 #               1700 1703 1713 1749 vborder 0
  56 #Then you can compute your values:
  57 #H front porch = 2608 - 2560 = 48
  58 #H sync = 2640 - 2608 = 32
  59 #H back porch = 2720 - 2640 = 80
  60 #V front porch = 1703 - 1700 = 3
  61 #V sync = 1713 - 1703 = 10
  62 #V back porch = 1749 - 1713 = 36
  63 #href_to_sync and vref_to_sync are from the vendor
  64 #this is just an example for a Pixel panel; other panels differ.
  65 # Here is a peppy panel:
  66 #  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
  67 #        h: width  1366 start 1502 end 1532 total 1592
  68 #        v: height  768 start  776 end  788 total  800
  69         register "href_to_sync" = "1"
  70         register "hfront_porch" = "136"
  71         register "hsync_width" = "30"
  72         register "hback_porch" = "60"
  73
  74         register "vref_to_sync" = "1"
  75         register "vfront_porch" = "8"
  76         register "vsync_width" = "12"
  77         register "vback_porch" = "12"
  78
  79         register "pixel_clock" = "76400000"
  80
  81         # link configurations
  82         register "lane_count" = "1"
  83         register "enhanced_framing" = "1"
  84         register "link_bw" = "10"
  85         # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
  86
  87         register "drive_current" = "0x40404040"
  88         register "preemphasis" = "0x0f0f0f0f"
  89         register "postcursor" = "0"
  90 end