src/mainboard/google/foster/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Google Inc.
   5  * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <bootblock_common.h>
  19 #include <console/console.h>
  20 #include <device/i2c.h>
  21 #include <soc/addressmap.h>
  22 #include <soc/clk_rst.h>
  23 #include <soc/clock.h>
  24 #include <soc/funitcfg.h>
  25 #include <soc/nvidia/tegra/i2c.h>
  26 #include <soc/padconfig.h>
  27 #include <soc/spi.h>    /* FIXME: move back to soc code? */
  28
  29 #include "pmic.h"
  30
  31 static const struct pad_config pmic_pads[] = {
  32         PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
  33         PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
  34 };
  35
  36 static const struct pad_config spiflash_pads[] = {
  37         /* QSPI fLash: mosi, miso, clk, cs0, hold, wp  */
  38         PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
  39         PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
  40         PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI),
  41         PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI),
  42         PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
  43         PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
  44 };
  45
  46 /********************* TPM ************************************/
  47 static const struct pad_config tpm_pads[] = {
  48         PAD_CFG_SFIO(GEN3_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
  49         PAD_CFG_SFIO(GEN3_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
  50 };
  51
  52 static const struct funit_cfg funits[] = {
  53         /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
  54         FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
  55         /* SPI flash at 24MHz on QSPI controller. */
  56         FUNIT_CFG(QSPI, PLLP, 24000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
  57         /* Foster has no TPM yet. This is for futurn TPM on I2C3  @ 400kHz. */
  58         FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
  59 };
  60
  61 static const struct pad_config uart_console_pads[] = {
  62         /* UARTA: tx, rx, rts, cts */
  63         PAD_CFG_SFIO(UART1_TX, PINMUX_PULL_NONE, UARTA),
  64         PAD_CFG_SFIO(UART1_RX, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UARTA),
  65         PAD_CFG_SFIO(UART1_RTS, PINMUX_PULL_UP, UARTA),
  66         PAD_CFG_SFIO(UART1_CTS, PINMUX_PULL_UP, UARTA),
  67 };
  68
  69 void bootblock_mainboard_early_init(void)
  70 {
  71         soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
  72 }
  73
  74 static void set_clock_sources(void)
  75 {
  76         /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
  77         write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
  78 }
  79
  80 void bootblock_mainboard_init(void)
  81 {
  82         set_clock_sources();
  83
  84         soc_configure_funits(funits, ARRAY_SIZE(funits));
  85
  86         i2c_init(I2CPWR_BUS);
  87         pmic_init(I2CPWR_BUS);
  88
  89         /* Foster has no TPM yet. This is for future TPM. */
  90         i2c_init(I2C3_BUS);
  91 }