2 * This file is part of the coreboot project.
4 * Copyright 2013 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 /* This code was originally generated using an i915tool program. It has been
21 #include <console/console.h>
23 #include <drivers/intel/gma/i915.h>
25 #include "mainboard.h"
27 /* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
28 void runio(struct intel_dp
*dp
);
30 void runio(struct intel_dp
*dp
)
34 intel_dp_wait_panel_power_control(0xabcd0008);
36 /* vbios spins at this point. Some haswell weirdness? */
37 intel_dp_wait_panel_power_control(0xabcd0008);
39 /* This should be a function like intel_panel_enable_backlight
40 However, we are not sure how the value 0x3a9 comes up.
41 It has to do something with PWM frequency */
42 gtt_write(BLC_PWM_CPU_CTL
,0x03a903a9);
43 gtt_write(BLC_PWM_PCH_CTL2
,0x03a903a9);
44 gtt_write(BLC_PWM_PCH_CTL1
,BLM_PCH_PWM_ENABLE
);
46 gtt_write(DEIIR
,0x00008000);
47 intel_dp_wait_reg(DEIIR
, 0x00000000);
49 gtt_write(DSPSTRIDE(dp
->plane
),dp
->stride
);
51 intel_dp_sink_dpms(dp
, 0);
53 intel_dp_get_max_downspread(dp
, &read_val
);
55 intel_dp_set_m_n_regs(dp
);
57 intel_dp_set_resolution(dp
);
59 gtt_write(PIPESRC(dp
->pipe
),dp
->pipesrc
);
60 gtt_write(PIPECONF(dp
->transcoder
),0x00000000);
61 gtt_write(PCH_TRANSCONF(dp
->pipe
),0x00000000);
63 mainboard_set_port_clk_dp(dp
);
64 gtt_write(DSPSTRIDE(dp
->plane
),dp
->stride
);
65 gtt_write(DSPCNTR(dp
->plane
),DISPLAY_PLANE_ENABLE
|DISPPLANE_BGRX888
);
66 gtt_write(DEIIR
,0x00000080);
68 gtt_write(TRANS_DDI_FUNC_CTL_EDP
,dp
->flags
);
69 gtt_write(PIPECONF(dp
->transcoder
),PIPECONF_ENABLE
|PIPECONF_DITHER_EN
);
71 intel_dp_wait_panel_power_control(0xabcd000a);
73 /* what is this doing? Not sure yet. */
74 intel_dp_i2c_write(dp
, 0x0);
75 intel_dp_i2c_read(dp
, &read_val
);
76 intel_dp_i2c_write(dp
, 0x04);
77 intel_dp_i2c_read(dp
, &read_val
);
78 intel_dp_i2c_write(dp
, 0x7e);
79 intel_dp_i2c_read(dp
, &read_val
);
81 /* this needs to be a call to a function */
82 gtt_write(DP_A
, DP_LINK_TRAIN_PAT_1
| DP_LINK_TRAIN_PAT_1_CPT
| DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
| DP_PORT_WIDTH_1
| DP_PLL_FREQ_270MHZ
| DP_SCRAMBLING_DISABLE_IRONLAKE
| DP_SYNC_VS_HIGH
|0x00000091);
83 gtt_write(DP_TP_CTL(dp
->port
),DP_TP_CTL_ENABLE
| DP_TP_CTL_ENHANCED_FRAME_ENABLE
);
84 gtt_write(DP_A
, DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
| DP_LINK_TRAIN_PAT_1_CPT
| DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
| DP_PORT_WIDTH_1
| DP_ENHANCED_FRAMING
| DP_PLL_FREQ_270MHZ
| DP_SCRAMBLING_DISABLE_IRONLAKE
| DP_SYNC_VS_HIGH
|0x80040091);
86 /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
87 gtt_write(PCH_PP_ON_DELAYS
, PANEL_PORT_SELECT_LVDS
|(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
88 gtt_write(PCH_PP_ON_DELAYS
, PANEL_PORT_SELECT_LVDS
|(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
91 intel_dp_set_lane_count(dp
);
93 mainboard_train_link(dp
);
95 /* need a function: intel_ddi_set_tp or similar */
96 gtt_write(DP_TP_CTL(dp
->port
),DP_TP_CTL_ENABLE
| DP_TP_CTL_ENHANCED_FRAME_ENABLE
| DP_TP_CTL_LINK_TRAIN_IDLE
);
97 gtt_write(DP_TP_CTL(dp
->port
),DP_TP_CTL_ENABLE
| DP_TP_CTL_ENHANCED_FRAME_ENABLE
| DP_TP_CTL_LINK_TRAIN_NORMAL
);
99 gtt_write(BLC_PWM_CPU_CTL
,0x03a903a9);
100 gtt_write(BLC_PWM_PCH_CTL2
,0x03a903a9);
101 gtt_write(BLC_PWM_PCH_CTL1
,0x80000000);
103 /* some of this is not needed. */
104 gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL
, DIGITAL_PORTA_HOTPLUG_ENABLE
);
106 gtt_write(SDEIIR
,0x00000000);
107 gtt_write(DEIIR
,0x00000000);
108 gtt_write(DEIIR
,0x00008000);
109 intel_dp_wait_reg(DEIIR
, 0x00000000);
111 gtt_write(DSPSTRIDE(dp
->plane
),dp
->stride
);
112 gtt_write(PIPESRC(dp
->pipe
),dp
->pipesrc
);
114 gtt_write(DEIIR
,0x00000080);
115 intel_dp_wait_reg(DEIIR
, 0x00000000);
117 gtt_write(DSPSTRIDE(dp
->plane
),dp
->stride
);
118 gtt_write(DSPCNTR(dp
->plane
),DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888
);
120 gtt_write(PCH_PP_CONTROL
,EDP_BLC_ENABLE
| PANEL_POWER_RESET
| PANEL_POWER_ON
);
122 gtt_write(SDEIIR
,0x00000000);
123 gtt_write(SDEIIR
,0x00000000);
124 gtt_write(DEIIR
,0x00000000);