?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / google / daisy / memory.c
blob009604b295fd6d96b0d49edea74bdd6e01441b5a
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Samsung Electronics
5 * Copyright 2013 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <console/console.h>
18 #include <soc/gpio.h>
19 #include <soc/setup.h>
20 #include <soc/dmc.h>
21 #include <soc/clk.h>
22 #include <stddef.h>
23 #include <stdlib.h>
24
25 const struct mem_timings mem_timings[] = {
26 {
27 .mem_manuf = MEM_MANUF_ELPIDA,
28 .mem_type = DDR_MODE_DDR3,
29 .frequency_mhz = 800,
30 .mpll_mdiv = 0x64,
31 .mpll_pdiv = 0x3,
32 .mpll_sdiv = 0x0,
33 .cpll_mdiv = 0xde,
34 .cpll_pdiv = 0x4,
35 .cpll_sdiv = 0x2,
36 .gpll_mdiv = 0x215,
37 .gpll_pdiv = 0xc,
38 .gpll_sdiv = 0x1,
39 .epll_mdiv = 0x60,
40 .epll_pdiv = 0x3,
41 .epll_sdiv = 0x3,
42 .vpll_mdiv = 0x96,
43 .vpll_pdiv = 0x3,
44 .vpll_sdiv = 0x2,
45
46 .bpll_mdiv = 0x64,
47 .bpll_pdiv = 0x3,
48 .bpll_sdiv = 0x0,
49 .use_bpll = 0,
50 .pclk_cdrex_ratio = 0x5,
51 .direct_cmd_msr = {
52 0x00020018, 0x00030000, 0x00010042, 0x00000d70
53 },
54 .timing_ref = 0x000000bb,
55 .timing_row = 0x8c36660f,
56 .timing_data = 0x3630580b,
57 .timing_power = 0x41000a44,
58 .phy0_dqs = 0x08080808,
59 .phy1_dqs = 0x08080808,
60 .phy0_dq = 0x08080808,
61 .phy1_dq = 0x08080808,
62 .phy0_tFS = 0x4,
63 .phy1_tFS = 0x4,
64 .phy0_pulld_dqs = 0xf,
65 .phy1_pulld_dqs = 0xf,
66
67 .lpddr3_ctrl_phy_reset = 0x1,
68 .ctrl_start_point = 0x10,
69 .ctrl_inc = 0x10,
70 .ctrl_start = 0x1,
71 .ctrl_dll_on = 0x1,
72 .ctrl_ref = 0x8,
73
74 .ctrl_force = 0x1a,
75 .ctrl_rdlat = 0x0b,
76 .ctrl_bstlen = 0x08,
77
78 .fp_resync = 0x8,
79 .iv_size = 0x7,
80 .dfi_init_start = 1,
81 .aref_en = 1,
82
83 .rd_fetch = 0x3,
84
85 .zq_mode_dds = 0x7,
86 .zq_mode_term = 0x1,
87 .zq_mode_noterm = 0,
88
89 /*
90 * Dynamic Clock: Always Running
91 * Memory Burst length: 8
92 * Number of chips: 1
93 * Memory Bus width: 32 bit
94 * Memory Type: DDR3
95 * Additional Latancy for PLL: 0 Cycle
96 */
97 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
98 DMC_MEMCONTROL_DPWRDN_DISABLE |
99 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
100 DMC_MEMCONTROL_TP_DISABLE |
101 DMC_MEMCONTROL_DSREF_ENABLE |
102 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
103 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
104 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
105 DMC_MEMCONTROL_NUM_CHIP_1 |
106 DMC_MEMCONTROL_BL_8 |
107 DMC_MEMCONTROL_PZQ_DISABLE |
108 DMC_MEMCONTROL_MRR_BYTE_7_0,
109 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
110 DMC_MEMCONFIGx_CHIP_COL_10 |
111 DMC_MEMCONFIGx_CHIP_ROW_15 |
112 DMC_MEMCONFIGx_CHIP_BANK_8,
113 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
114 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
115 .prechconfig_tp_cnt = 0xff,
116 .dpwrdn_cyc = 0xff,
117 .dsref_cyc = 0xffff,
118 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
119 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
120 DMC_CONCONTROL_RD_FETCH_DISABLE |
121 DMC_CONCONTROL_EMPTY_DISABLE |
122 DMC_CONCONTROL_AREF_EN_DISABLE |
123 DMC_CONCONTROL_IO_PD_CON_DISABLE,
124 .dmc_channels = 2,
125 .chips_per_channel = 2,
126 .chips_to_configure = 1,
127 .send_zq_init = 1,
128 .impedance = IMP_OUTPUT_DRV_30_OHM,
129 .gate_leveling_enable = 0,
130 }, {
131 .mem_manuf = MEM_MANUF_SAMSUNG,
132 .mem_type = DDR_MODE_DDR3,
133 .frequency_mhz = 800,
134 .mpll_mdiv = 0x64,
135 .mpll_pdiv = 0x3,
136 .mpll_sdiv = 0x0,
137 .cpll_mdiv = 0xde,
138 .cpll_pdiv = 0x4,
139 .cpll_sdiv = 0x2,
140 .gpll_mdiv = 0x215,
141 .gpll_pdiv = 0xc,
142 .gpll_sdiv = 0x1,
143 .epll_mdiv = 0x60,
144 .epll_pdiv = 0x3,
145 .epll_sdiv = 0x3,
146 .vpll_mdiv = 0x96,
147 .vpll_pdiv = 0x3,
148 .vpll_sdiv = 0x2,
149
150 .bpll_mdiv = 0x64,
151 .bpll_pdiv = 0x3,
152 .bpll_sdiv = 0x0,
153 .use_bpll = 0,
154 .pclk_cdrex_ratio = 0x5,
155 .direct_cmd_msr = {
156 0x00020018, 0x00030000, 0x00010000, 0x00000d70
157 },
158 .timing_ref = 0x000000bb,
159 .timing_row = 0x8c36660f,
160 .timing_data = 0x3630580b,
161 .timing_power = 0x41000a44,
162 .phy0_dqs = 0x08080808,
163 .phy1_dqs = 0x08080808,
164 .phy0_dq = 0x08080808,
165 .phy1_dq = 0x08080808,
166 .phy0_tFS = 0x8,
167 .phy1_tFS = 0x8,
168 .phy0_pulld_dqs = 0xf,
169 .phy1_pulld_dqs = 0xf,
170
171 .lpddr3_ctrl_phy_reset = 0x1,
172 .ctrl_start_point = 0x10,
173 .ctrl_inc = 0x10,
174 .ctrl_start = 0x1,
175 .ctrl_dll_on = 0x1,
176 .ctrl_ref = 0x8,
177
178 .ctrl_force = 0x1a,
179 .ctrl_rdlat = 0x0b,
180 .ctrl_bstlen = 0x08,
181
182 .fp_resync = 0x8,
183 .iv_size = 0x7,
184 .dfi_init_start = 1,
185 .aref_en = 1,
186
187 .rd_fetch = 0x3,
188
189 .zq_mode_dds = 0x5,
190 .zq_mode_term = 0x1,
191 .zq_mode_noterm = 1,
192
193 /*
194 * Dynamic Clock: Always Running
195 * Memory Burst length: 8
196 * Number of chips: 1
197 * Memory Bus width: 32 bit
198 * Memory Type: DDR3
199 * Additional Latancy for PLL: 0 Cycle
200 */
201 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
202 DMC_MEMCONTROL_DPWRDN_DISABLE |
203 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
204 DMC_MEMCONTROL_TP_DISABLE |
205 DMC_MEMCONTROL_DSREF_ENABLE |
206 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
207 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
208 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
209 DMC_MEMCONTROL_NUM_CHIP_1 |
210 DMC_MEMCONTROL_BL_8 |
211 DMC_MEMCONTROL_PZQ_DISABLE |
212 DMC_MEMCONTROL_MRR_BYTE_7_0,
213 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
214 DMC_MEMCONFIGx_CHIP_COL_10 |
215 DMC_MEMCONFIGx_CHIP_ROW_15 |
216 DMC_MEMCONFIGx_CHIP_BANK_8,
217 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
218 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
219 .prechconfig_tp_cnt = 0xff,
220 .dpwrdn_cyc = 0xff,
221 .dsref_cyc = 0xffff,
222 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
223 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
224 DMC_CONCONTROL_RD_FETCH_DISABLE |
225 DMC_CONCONTROL_EMPTY_DISABLE |
226 DMC_CONCONTROL_AREF_EN_DISABLE |
227 DMC_CONCONTROL_IO_PD_CON_DISABLE,
228 .dmc_channels = 2,
229 .chips_per_channel = 2,
230 .chips_to_configure = 1,
231 .send_zq_init = 1,
232 .impedance = IMP_OUTPUT_DRV_40_OHM,
233 .gate_leveling_enable = 1,
234 },
235 {
236 .mem_manuf = MEM_MANUF_ELPIDA,
237 .mem_type = DDR_MODE_DDR3,
238 .frequency_mhz = 780,
239 .mpll_mdiv = 0x64,
240 .mpll_pdiv = 0x3,
241 .mpll_sdiv = 0x0,
242 .cpll_mdiv = 0xde,
243 .cpll_pdiv = 0x4,
244 .cpll_sdiv = 0x2,
245 .gpll_mdiv = 0x215,
246 .gpll_pdiv = 0xc,
247 .gpll_sdiv = 0x1,
248 .epll_mdiv = 0x60,
249 .epll_pdiv = 0x3,
250 .epll_sdiv = 0x3,
251 .vpll_mdiv = 0x96,
252 .vpll_pdiv = 0x3,
253 .vpll_sdiv = 0x2,
254
255 .bpll_mdiv = 0x82,
256 .bpll_pdiv = 0x4,
257 .bpll_sdiv = 0x0,
258 .use_bpll = 1,
259 .pclk_cdrex_ratio = 0x5,
260 .direct_cmd_msr = {
261 0x00020018, 0x00030000, 0x00010042, 0x00000d70
262 },
263 .timing_ref = 0x000000bb,
264 .timing_row = 0x8c36660f,
265 .timing_data = 0x3630580b,
266 .timing_power = 0x41000a44,
267 .phy0_dqs = 0x08080808,
268 .phy1_dqs = 0x08080808,
269 .phy0_dq = 0x08080808,
270 .phy1_dq = 0x08080808,
271 .phy0_tFS = 0x4,
272 .phy1_tFS = 0x4,
273 .phy0_pulld_dqs = 0xf,
274 .phy1_pulld_dqs = 0xf,
275
276 .lpddr3_ctrl_phy_reset = 0x1,
277 .ctrl_start_point = 0x10,
278 .ctrl_inc = 0x10,
279 .ctrl_start = 0x1,
280 .ctrl_dll_on = 0x1,
281 .ctrl_ref = 0x8,
282
283 .ctrl_force = 0x1a,
284 .ctrl_rdlat = 0x0b,
285 .ctrl_bstlen = 0x08,
286
287 .fp_resync = 0x8,
288 .iv_size = 0x7,
289 .dfi_init_start = 1,
290 .aref_en = 1,
291
292 .rd_fetch = 0x3,
293
294 .zq_mode_dds = 0x7,
295 .zq_mode_term = 0x1,
296 .zq_mode_noterm = 0,
297
298 /*
299 * Dynamic Clock: Always Running
300 * Memory Burst length: 8
301 * Number of chips: 1
302 * Memory Bus width: 32 bit
303 * Memory Type: DDR3
304 * Additional Latancy for PLL: 0 Cycle
305 */
306 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
307 DMC_MEMCONTROL_DPWRDN_DISABLE |
308 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
309 DMC_MEMCONTROL_TP_DISABLE |
310 DMC_MEMCONTROL_DSREF_ENABLE |
311 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
312 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
313 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
314 DMC_MEMCONTROL_NUM_CHIP_1 |
315 DMC_MEMCONTROL_BL_8 |
316 DMC_MEMCONTROL_PZQ_DISABLE |
317 DMC_MEMCONTROL_MRR_BYTE_7_0,
318 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
319 DMC_MEMCONFIGx_CHIP_COL_10 |
320 DMC_MEMCONFIGx_CHIP_ROW_15 |
321 DMC_MEMCONFIGx_CHIP_BANK_8,
322 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
323 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
324 .prechconfig_tp_cnt = 0xff,
325 .dpwrdn_cyc = 0xff,
326 .dsref_cyc = 0xffff,
327 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
328 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
329 DMC_CONCONTROL_RD_FETCH_DISABLE |
330 DMC_CONCONTROL_EMPTY_DISABLE |
331 DMC_CONCONTROL_AREF_EN_DISABLE |
332 DMC_CONCONTROL_IO_PD_CON_DISABLE,
333 .dmc_channels = 2,
334 .chips_per_channel = 2,
335 .chips_to_configure = 1,
336 .send_zq_init = 1,
337 .impedance = IMP_OUTPUT_DRV_30_OHM,
338 .gate_leveling_enable = 0,
339 }, {
340 .mem_manuf = MEM_MANUF_SAMSUNG,
341 .mem_type = DDR_MODE_DDR3,
342 .frequency_mhz = 780,
343 .mpll_mdiv = 0x64,
344 .mpll_pdiv = 0x3,
345 .mpll_sdiv = 0x0,
346 .cpll_mdiv = 0xde,
347 .cpll_pdiv = 0x4,
348 .cpll_sdiv = 0x2,
349 .gpll_mdiv = 0x215,
350 .gpll_pdiv = 0xc,
351 .gpll_sdiv = 0x1,
352 .epll_mdiv = 0x60,
353 .epll_pdiv = 0x3,
354 .epll_sdiv = 0x3,
355 .vpll_mdiv = 0x96,
356 .vpll_pdiv = 0x3,
357 .vpll_sdiv = 0x2,
358
359 .bpll_mdiv = 0x82,
360 .bpll_pdiv = 0x4,
361 .bpll_sdiv = 0x0,
362 .use_bpll = 1,
363 .pclk_cdrex_ratio = 0x5,
364 .direct_cmd_msr = {
365 0x00020018, 0x00030000, 0x00010000, 0x00000d70
366 },
367 .timing_ref = 0x000000bb,
368 .timing_row = 0x8c36660f,
369 .timing_data = 0x3630580b,
370 .timing_power = 0x41000a44,
371 .phy0_dqs = 0x08080808,
372 .phy1_dqs = 0x08080808,
373 .phy0_dq = 0x08080808,
374 .phy1_dq = 0x08080808,
375 .phy0_tFS = 0x8,
376 .phy1_tFS = 0x8,
377 .phy0_pulld_dqs = 0xf,
378 .phy1_pulld_dqs = 0xf,
379
380 .lpddr3_ctrl_phy_reset = 0x1,
381 .ctrl_start_point = 0x10,
382 .ctrl_inc = 0x10,
383 .ctrl_start = 0x1,
384 .ctrl_dll_on = 0x1,
385 .ctrl_ref = 0x8,
386
387 .ctrl_force = 0x1a,
388 .ctrl_rdlat = 0x0b,
389 .ctrl_bstlen = 0x08,
390
391 .fp_resync = 0x8,
392 .iv_size = 0x7,
393 .dfi_init_start = 1,
394 .aref_en = 1,
395
396 .rd_fetch = 0x3,
397
398 .zq_mode_dds = 0x5,
399 .zq_mode_term = 0x1,
400 .zq_mode_noterm = 1,
401
402 /*
403 * Dynamic Clock: Always Running
404 * Memory Burst length: 8
405 * Number of chips: 1
406 * Memory Bus width: 32 bit
407 * Memory Type: DDR3
408 * Additional Latancy for PLL: 0 Cycle
409 */
410 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
411 DMC_MEMCONTROL_DPWRDN_DISABLE |
412 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
413 DMC_MEMCONTROL_TP_DISABLE |
414 DMC_MEMCONTROL_DSREF_ENABLE |
415 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
416 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
417 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
418 DMC_MEMCONTROL_NUM_CHIP_1 |
419 DMC_MEMCONTROL_BL_8 |
420 DMC_MEMCONTROL_PZQ_DISABLE |
421 DMC_MEMCONTROL_MRR_BYTE_7_0,
422 .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
423 DMC_MEMCONFIGx_CHIP_COL_10 |
424 DMC_MEMCONFIGx_CHIP_ROW_15 |
425 DMC_MEMCONFIGx_CHIP_BANK_8,
426 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
427 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
428 .prechconfig_tp_cnt = 0xff,
429 .dpwrdn_cyc = 0xff,
430 .dsref_cyc = 0xffff,
431 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
432 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
433 DMC_CONCONTROL_RD_FETCH_DISABLE |
434 DMC_CONCONTROL_EMPTY_DISABLE |
435 DMC_CONCONTROL_AREF_EN_DISABLE |
436 DMC_CONCONTROL_IO_PD_CON_DISABLE,
437 .dmc_channels = 2,
438 .chips_per_channel = 2,
439 .chips_to_configure = 1,
440 .send_zq_init = 1,
441 .impedance = IMP_OUTPUT_DRV_40_OHM,
442 .gate_leveling_enable = 1,
443 }
444 };
445
446 #define BOARD_ID0_GPIO 88 /* GPD0, pin 0 */
447 #define BOARD_ID1_GPIO 89 /* GPD0, pin 1 */
448
449 enum board_config {
450 DAISY_CONFIG_UNKNOWN = -1,
451 DAISY_CONFIG_SAMSUNG_EVT,
452 DAISY_CONFIG_ELPIDA_EVT,
453 DAISY_CONFIG_SAMSUNG_DVT,
454 DAISY_CONFIG_ELPIDA_DVT,
455 DAISY_CONFIG_SAMSUNG_PVT,
456 DAISY_CONFIG_ELPIDA_PVT,
457 DAISY_CONFIG_SAMSUNG_MP,
458 DAISY_CONFIG_ELPIDA_MP,
459 DAISY_CONFIG_RSVD,
460 };
461
462 struct {
463 enum mvl3 id0, id1;
464 enum board_config config;
465 } id_map[] = {
466 /* ID0 ID1 config */
467 { LOGIC_0, LOGIC_0, DAISY_CONFIG_SAMSUNG_MP },
468 { LOGIC_0, LOGIC_1, DAISY_CONFIG_ELPIDA_MP },
469 { LOGIC_1, LOGIC_0, DAISY_CONFIG_SAMSUNG_DVT },
470 { LOGIC_1, LOGIC_1, DAISY_CONFIG_ELPIDA_DVT },
471 { LOGIC_0, LOGIC_Z, DAISY_CONFIG_SAMSUNG_PVT },
472 { LOGIC_1, LOGIC_Z, DAISY_CONFIG_ELPIDA_PVT },
473 { LOGIC_Z, LOGIC_0, DAISY_CONFIG_SAMSUNG_MP },
474 { LOGIC_Z, LOGIC_Z, DAISY_CONFIG_ELPIDA_MP },
475 { LOGIC_Z, LOGIC_1, DAISY_CONFIG_RSVD },
476 };
477
478 static int board_get_config(void)
479 {
480 int i;
481 int id0, id1;
482 enum board_config config = DAISY_CONFIG_UNKNOWN;
483
484 id0 = gpio_read_mvl3(BOARD_ID0_GPIO);
485 id1 = gpio_read_mvl3(BOARD_ID1_GPIO);
486 if (id0 < 0 || id1 < 0)
487 return -1;
488
489 for (i = 0; i < ARRAY_SIZE(id_map); i++) {
490 if (id0 == id_map[i].id0 && id1 == id_map[i].id1) {
491 config = id_map[i].config;
492 break;
493 }
494 }
495
496 return config;
497 }
498
499 struct mem_timings *get_mem_timings(void)
500 {
501 int i;
502 enum board_config config;
503 enum ddr_mode mem_type;
504 unsigned int frequency_mhz;
505 enum mem_manuf mem_manuf;
506 const struct mem_timings *mem;
507
508 config = board_get_config();
509 switch (config) {
510 case DAISY_CONFIG_ELPIDA_EVT:
511 case DAISY_CONFIG_ELPIDA_DVT:
512 case DAISY_CONFIG_ELPIDA_PVT:
513 case DAISY_CONFIG_ELPIDA_MP:
514 mem_manuf = MEM_MANUF_ELPIDA;
515 mem_type = DDR_MODE_DDR3;
516 frequency_mhz = 800;
517 break;
518 case DAISY_CONFIG_SAMSUNG_EVT:
519 case DAISY_CONFIG_SAMSUNG_DVT:
520 case DAISY_CONFIG_SAMSUNG_PVT:
521 case DAISY_CONFIG_SAMSUNG_MP:
522 mem_manuf = MEM_MANUF_SAMSUNG;
523 mem_type = DDR_MODE_DDR3;
524 frequency_mhz = 800;
525 break;
526 default:
527 printk(BIOS_CRIT, "Unknown board configuration.\n");
528 return NULL;
529 }
530
531 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
532 i++, mem++) {
533 if (mem->mem_type == mem_type &&
534 mem->frequency_mhz == frequency_mhz &&
535 mem->mem_manuf == mem_manuf)
536 return (struct mem_timings *)mem;
537 }
538
539 return NULL;
540 }
ast, secure and flexible OpenSource firmware