src/mainboard/google/chell/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2015 Google Inc.
   6  * Copyright (C) 2015 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <cbfs.h>
  19 #include <console/console.h>
  20 #include <string.h>
  21 #include <ec/google/chromeec/ec.h>
  22 #include <soc/gpio.h>
  23 #include <soc/pei_data.h>
  24 #include <soc/pei_wrapper.h>
  25 #include <soc/romstage.h>
  26 #include "gpio.h"
  27 #include "spd/spd.h"
  28
  29 static void early_config_gpio(void)
  30 {
  31         /* This is a hack for FSP because it does things in MemoryInit()
  32          * which it shouldn't be. We have to prepare certain gpios here
  33          * because of the brokenness in FSP. */
  34         gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
  35 }
  36
  37 void mainboard_romstage_entry(struct romstage_params *params)
  38 {
  39         /* Ensure the EC and PD are in the right mode for recovery */
  40         google_chromeec_early_init();
  41
  42         early_config_gpio();
  43
  44         /* Fill out PEI DATA */
  45         mainboard_fill_pei_data(params->pei_data);
  46         mainboard_fill_spd_data(params->pei_data);
  47         /* Initliaze memory */
  48         romstage_common(params);
  49 }
  50
  51 void mainboard_memory_init_params(struct romstage_params *params,
  52                                   MEMORY_INIT_UPD *memory_params)
  53 {
  54         if (params->pei_data->spd_data[0][0][0] != 0) {
  55                 memory_params->MemorySpdPtr00 =
  56                                 (UINT32)(params->pei_data->spd_data[0][0]);
  57                 memory_params->MemorySpdPtr10 =
  58                                 (UINT32)(params->pei_data->spd_data[1][0]);
  59         }
  60         memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
  61                         sizeof(params->pei_data->dq_map[0]));
  62         memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
  63                         sizeof(params->pei_data->dq_map[1]));
  64         memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
  65                         sizeof(params->pei_data->dqs_map[0]));
  66         memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
  67                         sizeof(params->pei_data->dqs_map[1]));
  68         memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
  69                         sizeof(params->pei_data->RcompResistor));
  70         memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
  71                         sizeof(params->pei_data->RcompTarget));
  72         memory_params->MemorySpdDataLen = SPD_LEN;
  73         memory_params->DqPinsInterleaved = FALSE;
  74 }