src/mainboard/google/bolt/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright 2012 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <cpu/x86/smm.h>
  20 #include <southbridge/intel/lynxpoint/lp_gpio.h>
  21 #include <southbridge/intel/lynxpoint/nvs.h>
  22 #include <southbridge/intel/lynxpoint/pch.h>
  23 #include <southbridge/intel/lynxpoint/me.h>
  24 #include <northbridge/intel/haswell/haswell.h>
  25 #include <cpu/intel/haswell/haswell.h>
  26 #include <elog.h>
  27
  28 /* Include EC functions */
  29 #include <ec/google/chromeec/ec.h>
  30 #include "ec.h"
  31
  32 static u8 mainboard_smi_ec(void)
  33 {
  34         u8 cmd = google_chromeec_get_event();
  35         u32 pm1_cnt;
  36
  37 #if CONFIG_ELOG_GSMI
  38         /* Log this event */
  39         if (cmd)
  40                 elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
  41 #endif
  42
  43         switch (cmd) {
  44         case EC_HOST_EVENT_LID_CLOSED:
  45                 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
  46
  47                 /* Go to S5 */
  48                 pm1_cnt = inl(get_pmbase() + PM1_CNT);
  49                 pm1_cnt |= (0xf << 10);
  50                 outl(pm1_cnt, get_pmbase() + PM1_CNT);
  51                 break;
  52         }
  53
  54         return cmd;
  55 }
  56
  57 /* gpi_sts is GPIO 47:32 */
  58 void mainboard_smi_gpi(u32 gpi_sts)
  59 {
  60         if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
  61                 /* Process all pending events */
  62                 while (mainboard_smi_ec() != 0);
  63         }
  64 }
  65
  66 static void bolt_wlan_off(void)
  67 {
  68         u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
  69         u32 gpio_conf;
  70
  71         /* Make sure pin is owned by GPIO subsystem and not ACPI */
  72         gpio_conf = inl(gpio_base + GPIO_OWNER(0));
  73         gpio_conf |= GPIO_OWNER_GPIO << 29;
  74         outl(gpio_conf, gpio_base + GPIO_OWNER(0));
  75
  76         /* Set GPIO29 config to only be reset on RSMRST */
  77         gpio_conf = inl(gpio_base + GPIO_RESET(0));
  78         gpio_conf |= GPIO_RESET_RSMRST << 29;
  79         outl(gpio_conf, gpio_base + GPIO_RESET(0));
  80
  81         /* Set WLAN_OFF_L (GPIO29) as Output GPIO driven high */
  82         gpio_conf = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH;
  83         outl(gpio_conf, gpio_base + GPIO_CONFIG0(29));
  84 }
  85
  86 void mainboard_smi_sleep(u8 slp_typ)
  87 {
  88         /* Disable USB charging if required */
  89         switch (slp_typ) {
  90         case 3:
  91                 if (smm_get_gnvs()->s3u0 == 0)
  92                         google_chromeec_set_usb_charge_mode(
  93                                 0, USB_CHARGE_MODE_DISABLED);
  94                 if (smm_get_gnvs()->s3u1 == 0)
  95                         google_chromeec_set_usb_charge_mode(
  96                                 1, USB_CHARGE_MODE_DISABLED);
  97                 break;
  98         case 5:
  99                 if (smm_get_gnvs()->s5u0 == 0)
 100                         google_chromeec_set_usb_charge_mode(
 101                                 0, USB_CHARGE_MODE_DISABLED);
 102                 if (smm_get_gnvs()->s5u1 == 0)
 103                         google_chromeec_set_usb_charge_mode(
 104                                 1, USB_CHARGE_MODE_DISABLED);
 105                 break;
 106         }
 107
 108         /* Set WLAN_OFF GPIO state */
 109         bolt_wlan_off();
 110
 111         /* Disable SCI and SMI events */
 112         google_chromeec_set_smi_mask(0);
 113         google_chromeec_set_sci_mask(0);
 114
 115         /* Clear pending events that may trigger immediate wake */
 116         while (google_chromeec_get_event() != 0);
 117
 118         /* Enable wake events */
 119         google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 120 }
 121
 122
 123 static int mainboard_finalized = 0;
 124
 125 int mainboard_smi_apmc(u8 apmc)
 126 {
 127         switch (apmc) {
 128         case APM_CNT_FINALIZE:
 129                 if (mainboard_finalized) {
 130                         printk(BIOS_DEBUG, "SMI#: Already finalized\n");
 131                         return 0;
 132                 }
 133
 134                 intel_pch_finalize_smm();
 135                 intel_northbridge_haswell_finalize_smm();
 136                 intel_cpu_haswell_finalize_smm();
 137
 138                 mainboard_finalized = 1;
 139                 break;
 140         case APM_CNT_ACPI_ENABLE:
 141                 google_chromeec_set_smi_mask(0);
 142                 /* Clear all pending events */
 143                 while (google_chromeec_get_event() != 0);
 144                 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 145                 break;
 146         case APM_CNT_ACPI_DISABLE:
 147                 google_chromeec_set_sci_mask(0);
 148                 /* Clear all pending events */
 149                 while (google_chromeec_get_event() != 0);
 150                 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 151                 break;
 152         }
 153         return 0;
 154 }