2 * This file is part of the coreboot project.
4 * Copyright (C) 2014 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <console/console.h>
21 #include <soc/pei_data.h>
22 #include <soc/romstage.h>
23 #include <ec/google/chromeec/ec.h>
24 #include <mainboard/google/auron/ec.h>
25 #include <mainboard/google/auron/gpio.h>
26 #include <mainboard/google/auron/spd/spd.h>
28 static void mainboard_print_spd_info(uint8_t spd
[])
30 const int spd_banks
[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
31 const int spd_capmb
[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
32 const int spd_rows
[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
33 const int spd_cols
[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
34 const int spd_ranks
[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
35 const int spd_devw
[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
36 const int spd_busw
[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
37 char spd_name
[SPD_PART_LEN
+1] = { 0 };
39 int banks
= spd_banks
[(spd
[SPD_DENSITY_BANKS
] >> 4) & 7];
40 int capmb
= spd_capmb
[spd
[SPD_DENSITY_BANKS
] & 7] * 256;
41 int rows
= spd_rows
[(spd
[SPD_ADDRESSING
] >> 3) & 7];
42 int cols
= spd_cols
[spd
[SPD_ADDRESSING
] & 7];
43 int ranks
= spd_ranks
[(spd
[SPD_ORGANIZATION
] >> 3) & 7];
44 int devw
= spd_devw
[spd
[SPD_ORGANIZATION
] & 7];
45 int busw
= spd_busw
[spd
[SPD_BUS_DEV_WIDTH
] & 7];
48 printk(BIOS_INFO
, "SPD: module type is ");
49 switch (spd
[SPD_DRAM_TYPE
]) {
51 printk(BIOS_INFO
, "DDR3\n");
54 printk(BIOS_INFO
, "LPDDR3\n");
57 printk(BIOS_INFO
, "Unknown (%02x)\n", spd
[SPD_DRAM_TYPE
]);
61 /* Module Part Number */
62 memcpy(spd_name
, &spd
[SPD_PART_OFF
], SPD_PART_LEN
);
63 spd_name
[SPD_PART_LEN
] = 0;
64 printk(BIOS_INFO
, "SPD: module part is %s\n", spd_name
);
66 printk(BIOS_INFO
, "SPD: banks %d, ranks %d, rows %d, columns %d, "
67 , banks
, ranks
, rows
, cols
);
68 printk(BIOS_INFO
, "density %d Mb\n", capmb
);
70 printk(BIOS_INFO
, "SPD: device width %d bits, bus width %d bits\n",
73 if (capmb
> 0 && busw
> 0 && devw
> 0 && ranks
> 0) {
74 /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
75 printk(BIOS_INFO
, "SPD: module size is %u MB (per channel)\n",
76 capmb
/ 8 * busw
/ devw
* ranks
);
80 /* Copy SPD data for on-board memory */
81 void mainboard_fill_spd_data(struct pei_data
*pei_data
)
93 spd_gpio
[0] = get_gpio(SPD_GPIO_BIT0
);
94 spd_gpio
[1] = get_gpio(SPD_GPIO_BIT1
);
95 spd_gpio
[2] = get_gpio(SPD_GPIO_BIT2
);
97 spd_index
= spd_gpio
[2] << 2 | spd_gpio
[1] << 1 | spd_gpio
[0];
99 printk(BIOS_DEBUG
, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
101 spd_bits
[2], spd_gpio
[2],
102 spd_bits
[1], spd_gpio
[1],
103 spd_bits
[0], spd_gpio
[0]);
105 spd_file
= cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len
);
107 die("SPD data not found.");
109 if (spd_file_len
< ((spd_index
+ 1) * SPD_LEN
)) {
110 printk(BIOS_ERR
, "SPD index override to 0 - old hardware?\n");
114 if (spd_file_len
< SPD_LEN
)
115 die("Missing SPD data.");
117 memcpy(pei_data
->spd_data
[0][0],
118 spd_file
+ (spd_index
* SPD_LEN
), SPD_LEN
);
119 /* Index 0-2 are 4GB config with both CH0 and CH1.
120 * Index 4-6 are 2GB config with CH0 only. */
122 pei_data
->dimm_channel1_disabled
= 3;
124 memcpy(pei_data
->spd_data
[1][0],
125 spd_file
+ (spd_index
* SPD_LEN
), SPD_LEN
);
127 /* Make sure a valid SPD was found */
128 if (pei_data
->spd_data
[0][0][0] == 0)
129 die("Invalid SPD data.");
131 mainboard_print_spd_info(pei_data
->spd_data
[0][0]);