src/mainboard/gizmosphere/gizmo2/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <string.h>
  18 #include <device/pci_def.h>
  19 #include <device/pci_ids.h>
  20 #include <arch/acpi.h>
  21 #include <arch/io.h>
  22 #include <arch/stages.h>
  23 #include <device/pnp_def.h>
  24 #include <arch/cpu.h>
  25 #include <cpu/x86/lapic.h>
  26 #include <console/console.h>
  27 #include <commonlib/loglevel.h>
  28 #include <cpu/amd/car.h>
  29 #include <northbridge/amd/agesa/agesawrapper.h>
  30 #include <cpu/x86/bist.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <southbridge/amd/agesa/hudson/hudson.h>
  33 #include <cpu/amd/agesa/s3_resume.h>
  34 #include "cbmem.h"
  35
  36
  37 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  38 {
  39         u32 val;
  40
  41         /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
  42          *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
  43          *  even though the register is not documented in the Kabini BKDG.
  44          *  Otherwise the serial output is bad code.
  45          */
  46         outb(0xD2, 0xcd6);
  47         outb(0x00, 0xcd7);
  48
  49         amd_initmmio();
  50
  51         /* Set LPC decode enables. */
  52         pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
  53         pci_write_config32(dev, 0x44, 0xff03ffd5);
  54
  55         hudson_lpc_port80();
  56
  57         if (!cpu_init_detectedx && boot_cpu()) {
  58                 post_code(0x30);
  59
  60                 post_code(0x31);
  61                 console_init();
  62         }
  63
  64         /* Halt if there was a built in self test failure */
  65         post_code(0x34);
  66         report_bist_failure(bist);
  67
  68         /* Load MPB */
  69         val = cpuid_eax(1);
  70         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
  71         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
  72
  73         /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
  74         int i;
  75         for(i = 0; i < 200000; i++)
  76                 val = inb(0xcd6);
  77
  78         post_code(0x37);
  79         agesawrapper_amdinitreset();
  80         post_code(0x38);
  81         printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
  82
  83         post_code(0x39);
  84
  85         agesawrapper_amdinitearly();
  86         int s3resume = acpi_is_wakeup_s3();
  87         if (!s3resume) {
  88                 post_code(0x40);
  89                 agesawrapper_amdinitpost();
  90                 post_code(0x41);
  91                 agesawrapper_amdinitenv();
  92                 /* TODO: Disable cache is not ok. */
  93                 disable_cache_as_ram();
  94         } else { /* S3 detect */
  95                 printk(BIOS_INFO, "S3 detected\n");
  96
  97                 post_code(0x60);
  98                 agesawrapper_amdinitresume();
  99
 100                 amd_initcpuio();
 101                 agesawrapper_amds3laterestore();
 102
 103                 post_code(0x61);
 104                 prepare_for_resume();
 105         }
 106
 107         outb(0xEA, 0xCD6);
 108         outb(0x1, 0xcd7);
 109
 110         post_code(0x50);
 111         copy_and_run();
 112
 113         post_code(0x54);  /* Should never see this post code. */
 114 }