src/mainboard/gizmosphere/gizmo2/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC
   6  * All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <arch/io.h>
  22 #include <cpu/x86/msr.h>
  23 #include <cpu/amd/mtrr.h>
  24 #include <device/pci_def.h>
  25 #include <arch/acpi.h>
  26 #include <southbridge/amd/agesa/hudson/pci_devs.h>
  27 #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
  28 #include <southbridge/amd/common/amd_pci_util.h>
  29 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
  30 #include <northbridge/amd/agesa/BiosCallOuts.h>
  31 #include <cpu/amd/agesa/s3_resume.h>
  32 #include <northbridge/amd/agesa/agesawrapper.h>
  33
  34 /***********************************************************
  35  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  36  * This table is responsible for physically routing the PIC and
  37  * IOAPIC IRQs to the different PCI devices on the system.  It
  38  * is read and written via registers 0xC00/0xC01 as an
  39  * Index/Data pair.  These values are chipset and mainboard
  40  * dependent and should be updated accordingly.
  41  *
  42  * These values are used by the PCI configuration space,
  43  * MP Tables.  TODO: Make ACPI use these values too.
  44  */
  45 const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  46         /* INTA# - INTH# */
  47         [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  48         /* Misc-nil,0,1,2, INT from Serial irq */
  49         [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  50         /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
  51         [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  52         /* IMC INT0 - 5 */
  53         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  54         /* USB Devs 18/19/22 INTA-C */
  55         [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  56         /* SATA */
  57         [0x41] = 0x0F,
  58 };
  59
  60 const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  61         /* INTA# - INTH# */
  62         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
  63         /* Misc-nil,0,1,2, INT from Serial irq */
  64         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  65         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
  66         [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
  67         /* IMC INT0 - 5 */
  68         [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
  69         /* USB Devs 18/19/20/22 INTA-C */
  70         [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
  71         /* SATA */
  72         [0x41] = 0x13
  73 };
  74
  75 /*
  76  * This table defines the index into the picr/intr_data
  77  * tables for each device.  Any enabled device and slot
  78  * that uses hardware interrupts should have an entry
  79  * in this table to define its index into the FCH
  80  * PCI_INTR register 0xC00/0xC01.  This index will define
  81  * the interrupt that it should use.  Putting PIRQ_A into
  82  * the PIN A index for a device will tell that device to
  83  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  84  */
  85 static const struct pirq_struct mainboard_pirq_data[] = {
  86         /* {PCI_devfn,  {PIN A, PIN B, PIN C, PIN D}}, */
  87         {GFX_DEVFN,     {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},                   /* VGA:         01.0 */
  88         {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},                       /* Audio:       01.1 */
  89         {NB_PCIE_PORT1_DEVFN,   {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},      /* x4 PCIe:     02.1 */
  90         {NB_PCIE_PORT2_DEVFN,   {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},      /* mPCIe:       02.2 */
  91         {NB_PCIE_PORT3_DEVFN,   {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}},      /* NIC:         02.3 */
  92         {NB_PCIE_PORT4_DEVFN,   {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}},      /* Edge:        02.4 */
  93         {NB_PCIE_PORT5_DEVFN,   {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}},      /* Edge:        02.5 */
  94         {XHCI_DEVFN,    {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},           /* XHCI:        10.0 */
  95         {SATA_DEVFN,    {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},        /* SATA:        11.0 */
  96         {OHCI1_DEVFN,   {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* OHCI1:       12.0 */
  97         {EHCI1_DEVFN,   {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},       /* EHCI1:       12.2 */
  98         {OHCI2_DEVFN,   {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* OHCI2:       13.0 */
  99         {EHCI2_DEVFN,   {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},       /* EHCI2:       13.2 */
 100         {SMBUS_DEVFN,   {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* SMBUS:       14.0 */
 101         {HDA_DEVFN,             {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},         /* HDA:         14.2 */
 102         {SD_DEVFN,              {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},          /* SD:          14.7 */
 103 };
 104
 105 const u8 *picr_data = mainboard_picr_data;
 106 const u8 *intr_data = mainboard_intr_data;
 107
 108 /* PIRQ Setup */
 109 static void pirq_setup(void)
 110 {
 111         pirq_data_ptr = mainboard_pirq_data;
 112         pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
 113         intr_data_ptr = mainboard_intr_data;
 114         picr_data_ptr = mainboard_picr_data;
 115 }
 116
 117 /**********************************************
 118  * enable the dedicated function in mainboard.
 119  **********************************************/
 120 static void mainboard_enable(device_t dev)
 121 {
 122         printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 123
 124         if (acpi_is_wakeup_s3())
 125                 agesawrapper_fchs3earlyrestore();
 126
 127         /* Initialize the PIRQ data structures for consumption */
 128         pirq_setup();
 129 }
 130
 131 struct chip_operations mainboard_ops = {
 132         .enable_dev = mainboard_enable,
 133 };