src/mainboard/gizmosphere/gizmo/platform_cfg.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17
  18 #ifndef _PLATFORM_CFG_H_
  19 #define _PLATFORM_CFG_H_
  20
  21 /* Gizmo has no legacy P/S2 controller */
  22 #define LEGACY_FREE             1
  23
  24 /**
  25  * @def BIOS_SIZE
  26  *      BIOS_SIZE_{1,2,4,8,16}M
  27  *
  28  * In SB800, default ROM size is 1M Bytes, if your platform ROM
  29  * bigger than 1M you have to set the ROM size outside CIMx module and
  30  * before AGESA module get call.
  31  */
  32 #ifndef BIOS_SIZE
  33 #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
  34 #endif /* BIOS_SIZE */
  35
  36 /**
  37  * @def SPREAD_SPECTRUM
  38  * @brief
  39  *  0 - Disable Spread Spectrum function
  40  *  1 - Enable  Spread Spectrum function
  41  */
  42 #define SPREAD_SPECTRUM                 0
  43
  44 /**
  45  * @def SB_HPET_TIMER
  46  * @brief
  47  *  0 - Disable hpet
  48  *  1 - Enable  hpet
  49  */
  50 #define HPET_TIMER                      1
  51
  52 /**
  53  * @def USB_CONFIG
  54  * @brief bit[0-6] used to control USB
  55  *   0 - Disable
  56  *   1 - Enable
  57  *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
  58  *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
  59  *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
  60  *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
  61  *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
  62  *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
  63  *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
  64  */
  65 #define USB_CONFIG              0x7F
  66
  67 /**
  68  * @def PCI_CLOCK_CTRL
  69  * @brief bit[0-4] used for PCI Slots Clock Control,
  70  *   0 - disable
  71  *   1 - enable
  72  *  PCI SLOT 0 define at BIT0
  73  *  PCI SLOT 1 define at BIT1
  74  *  PCI SLOT 2 define at BIT2
  75  *  PCI SLOT 3 define at BIT3
  76  *  PCI SLOT 4 define at BIT4
  77  */
  78 #define PCI_CLOCK_CTRL                  0x00 /* PCI clocks aren't used on Gizmo */
  79
  80 /**
  81  * @def SATA_CONTROLLER
  82  * @brief INCHIP Sata Controller
  83  */
  84 #define SATA_CONTROLLER         CIMX_OPTION_ENABLED
  85
  86 /**
  87  * @def SATA_MODE
  88  * @brief INCHIP Sata Controller Mode
  89  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  90  */
  91 #define SATA_MODE                       CONFIG_SB800_SATA_MODE
  92
  93 /**
  94  * @brief INCHIP Sata IDE Controller Mode
  95  */
  96 #define IDE_LEGACY_MODE                 0
  97 #define IDE_NATIVE_MODE                 1
  98
  99 /**
 100  * @def SATA_IDE_MODE
 101  * @brief INCHIP Sata IDE Controller Mode
 102  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
 103  */
 104 #define SATA_IDE_MODE                   IDE_LEGACY_MODE
 105
 106 /**
 107  * @def EXTERNAL_CLOCK
 108  * @brief 00/10: Reference clock from crystal oscillator via
 109  *  PAD_XTALI and PAD_XTALO
 110  *
 111  * @def INTERNAL_CLOCK
 112  * @brief 01/11: Reference clock from internal clock through
 113  *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
 114  */
 115 #define EXTERNAL_CLOCK          0x00
 116 #define INTERNAL_CLOCK          0x01
 117
 118 /* NOTE: inagua have to using internal clock,
 119  * otherwise can not detect sata drive
 120  */
 121 #define SATA_CLOCK_SOURCE       INTERNAL_CLOCK
 122
 123 /**
 124  * @def SATA_PORT_MULT_CAP_RESERVED
 125  * @brief 1 ON, 0 0FF
 126  */
 127 #define SATA_PORT_MULT_CAP_RESERVED     1
 128
 129
 130 /**
 131  * @def   AZALIA_AUTO
 132  * @brief Detect Azalia controller automatically.
 133  *
 134  * @def   AZALIA_DISABLE
 135  * @brief Disable Azalia controller.
 136
 137  * @def   AZALIA_ENABLE
 138  * @brief Enable Azalia controller.
 139  */
 140 #define AZALIA_AUTO                     0
 141 #define AZALIA_DISABLE                  1
 142 #define AZALIA_ENABLE                   2
 143
 144 /**
 145  * @brief INCHIP HDA controller
 146  */
 147 #define AZALIA_CONTROLLER               AZALIA_AUTO
 148
 149 /**
 150  * @def AZALIA_PIN_CONFIG
 151  * @brief
 152  *  0 - disable
 153  *  1 - enable
 154  */
 155 #define AZALIA_PIN_CONFIG               1
 156
 157 /**
 158  * @def AZALIA_SDIN_PIN
 159  * @brief
 160  *  SDIN0 is define at BIT0 & BIT1
 161  *   00 - GPIO PIN
 162  *   01 - Reserved
 163  *   10 - As a Azalia SDIN pin
 164  *  SDIN1 is define at BIT2 & BIT3
 165  *  SDIN2 is define at BIT4 & BIT5
 166  *  SDIN3 is define at BIT6 & BIT7
 167  */
 168 //#define AZALIA_SDIN_PIN               0xAA
 169 #define AZALIA_SDIN_PIN                 0x2A
 170
 171 /**
 172  * @def GPP_CONTROLLER
 173  */
 174 #define GPP_CONTROLLER                  CIMX_OPTION_ENABLED
 175
 176 /**
 177  * @def GPP_CFGMODE
 178  * @brief GPP Link Configuration
 179  * four possible configuration:
 180  *  GPP_CFGMODE_X4000
 181  *  GPP_CFGMODE_X2200
 182  *  GPP_CFGMODE_X2110
 183  *  GPP_CFGMODE_X1111
 184  */
 185 #define GPP_CFGMODE                     GPP_CFGMODE_X1111
 186
 187 /**
 188  * @def NB_SB_GEN2
 189  *    0  - Disable
 190  *    1  - Enable
 191  */
 192 #define NB_SB_GEN2                      TRUE
 193
 194 /**
 195  * @def SB_GPP_GEN2
 196  *    0  - Disable
 197  *    1  - Enable
 198  */
 199 #define SB_GPP_GEN2                     TRUE
 200
 201 /**
 202  * @def SB_GPP_UNHIDE_PORTS
 203  *    TRUE   - ports visible always, even port empty
 204  *    FALSE  - ports invisible if port empty
 205  */
 206 #define SB_GPP_UNHIDE_PORTS             TRUE
 207
 208 /**
 209  * @def   GEC_CONFIG
 210  *    0  - Enable
 211  *    1  - Disable
 212  */
 213 #define GEC_CONFIG                      0
 214
 215 const static CODECENTRY gizmo_codec_alc272[] =
 216 {
 217         /* NID, PinConfig */
 218         {0x11, 0x411111F0},     /* S/PDIF-OUT2 unused */
 219         {0x12, 0x411111F0},     /* DMIC-1/2 unused */
 220         {0x13, 0x411111F0},     /* DMIC-3/4 unused */
 221         {0x14, 0x411111F0},     /* LOUT-1 unused */
 222         {0x15, 0x21000100},     /* LOUT2 - to Explorer */
 223         {0x17, 0x411111F0},     /* MONO-OUT unused */
 224         {0x18, 0x01A15010},     /* MIC1 */
 225         {0x19, 0x411111F0},     /* MIC2 unused */
 226         {0x1A, 0x01013010},     /* LINE1 */
 227         {0x1B, 0x21800101},     /* LINE2 from Explorer */
 228         {0x1D, 0x40100000},     /* PCBEEP */
 229         {0x1E, 0x411111F0},     /* S/PDIF-OUT1 unused */
 230         {0x21, 0x01214010},     /* HPOUT */
 231         {0xff, 0xffffffff}      /* end of table */
 232 };
 233
 234 static const CODECTBLLIST codec_tablelist[] =
 235 {
 236         {0x010ec0272, (CODECENTRY*)&gizmo_codec_alc272[0]},
 237         {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
 238 };
 239
 240 /**
 241  * @def AZALIA_OEM_VERB_TABLE
 242  *  Mainboard specific codec verb table list
 243  */
 244 #define AZALIA_OEM_VERB_TABLE           (&codec_tablelist[0])
 245
 246 /* set up an ACPI preferred power management profile */
 247 /*  from acpi.h
 248  *      PM_UNSPECIFIED          = 0,
 249  *      PM_DESKTOP              = 1,
 250  *      PM_MOBILE               = 2,
 251  *      PM_WORKSTATION          = 3,
 252  *      PM_ENTERPRISE_SERVER    = 4,
 253  *      PM_SOHO_SERVER          = 5,
 254  *      PM_APPLIANCE_PC         = 6,
 255  *      PM_PERFORMANCE_SERVER   = 7,
 256  *      PM_TABLET               = 8
 257  */
 258 #define FADT_PM_PROFILE 1
 259
 260 #endif