src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #define SUPERIO_BASE 0x2e
  17 #define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
  18 #define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
  19 #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
  20
  21 #include <arch/io.h>
  22 #include <device/pci_def.h>
  23 #include <device/pnp_def.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <arch/acpi.h>
  26 #include <console/console.h>
  27 #include <superio/ite/it8728f/it8728f.h>
  28 #include <superio/ite/common/ite.h>
  29 #include <northbridge/intel/sandybridge/sandybridge.h>
  30 #include <northbridge/intel/sandybridge/raminit_native.h>
  31 #include <southbridge/intel/bd82x6x/pch.h>
  32 #include <southbridge/intel/bd82x6x/gpio.h>
  33 #include <arch/cpu.h>
  34 #include <cpu/x86/msr.h>
  35
  36 static void it8728f_b75md3h_disable_reboot(device_t dev)
  37 {
  38         /* GPIO SIO settings */
  39         ite_reg_write(dev, 0xEF, 0x7E); // magic
  40
  41         ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
  42         ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
  43         ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
  44         ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
  45         ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
  46         ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
  47         ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
  48         ite_reg_write(dev, 0xe9, 0x27); // bus select disable
  49         ite_reg_write(dev, 0xf0, 0x10); // ?
  50         ite_reg_write(dev, 0xf1, 0x42); // ?
  51         ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
  52
  53         /* EC SIO settings */
  54         ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
  55         ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
  56         ite_reg_write(IT8728F_EC, 0xf9, 0x48);
  57         ite_reg_write(IT8728F_EC, 0x60, 0x0a);
  58         ite_reg_write(IT8728F_EC, 0x61, 0x30);
  59         ite_reg_write(IT8728F_EC, 0x62, 0x0a);
  60         ite_reg_write(IT8728F_EC, 0x63, 0x20);
  61         ite_reg_write(IT8728F_EC, 0x30, 0x01);
  62 }
  63
  64 void rcba_config(void)
  65 {
  66 /*
  67         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
  68         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
  69         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
  70
  71         outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
  72
  73         RCBA32(0x3500) = 0x2000035f;
  74         RCBA32(0x3504) = 0x2000035f;
  75         RCBA32(0x3508) = 0x2000035f;
  76         RCBA32(0x350c) = 0x2000035f;
  77         RCBA32(0x3510) = 0x2000035f;
  78         RCBA32(0x3514) = 0x2000035f;
  79         RCBA32(0x3518) = 0x2000035f;
  80         RCBA32(0x351c) = 0x2000035f;
  81         RCBA32(0x3520) = 0x2000035f;
  82         RCBA32(0x3524) = 0x2000035f;
  83         RCBA32(0x3528) = 0x2000035f;
  84         RCBA32(0x352c) = 0x2000035f;
  85         RCBA32(0x3530) = 0x2000035f;
  86         RCBA32(0x3534) = 0x2000035f;
  87         RCBA32(0x3560) = 0x024c8001;
  88         RCBA32(0x3564) = 0x000024a3;
  89         RCBA32(0x3568) = 0x00040002;
  90         RCBA32(0x356c) = 0x01000050;
  91         RCBA32(0x3570) = 0x02000662;
  92         RCBA32(0x3574) = 0x18000f9f;
  93         RCBA32(0x3578) = 0x1800ff4f;
  94         RCBA32(0x357c) = 0x0001d530;
  95         RCBA32(0x35a0) = 0xc0300c03;
  96         RCBA32(0x35a4) = 0x00241803;
  97
  98         pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
  99
 100         outw (0x0000, DEFAULT_PMBASE | 0x003c);
 101
 102         RCBA32(0x2240) = 0x00330e71;
 103         RCBA32(0x2244) = 0x003f0eb1;
 104         RCBA32(0x2248) = 0x002102cd;
 105         RCBA32(0x224c) = 0x00f60000;
 106         RCBA32(0x2250) = 0x00020000;
 107         RCBA32(0x2254) = 0x00e3004c;
 108         RCBA32(0x2258) = 0x00e20bef;
 109         RCBA32(0x2260) = 0x003304ed;
 110         RCBA32(0x2278) = 0x001107c1;
 111         RCBA32(0x227c) = 0x001d07e9;
 112         RCBA32(0x2280) = 0x00e20000;
 113         RCBA32(0x2284) = 0x00ee0000;
 114         RCBA32(0x2288) = 0x005b05d3;
 115         RCBA32(0x2318) = 0x04b8ff2e;
 116         RCBA32(0x231c) = 0x03930f2e;
 117 //      RCBA32(0x3418) = 0x1fee1fe1;
 118         RCBA32(0x3808) = 0x005044a3;
 119         RCBA32(0x3810) = 0x52410000;
 120         RCBA32(0x3814) = 0x0000008a;
 121         RCBA32(0x3818) = 0x00000006;
 122         RCBA32(0x381c) = 0x0000072e;
 123         RCBA32(0x3820) = 0x0000000a;
 124         RCBA32(0x3824) = 0x00000123;
 125         RCBA32(0x3828) = 0x00000009;
 126         RCBA32(0x382c) = 0x00000001;
 127         RCBA32(0x3834) = 0x0000061a;
 128         RCBA32(0x3838) = 0x00000003;
 129         RCBA32(0x383c) = 0x00000a76;
 130         RCBA32(0x3840) = 0x00000004;
 131         RCBA32(0x3844) = 0x0000e5e4;
 132         RCBA32(0x3848) = 0x0000000e;
 133 */
 134         /* Disable unused devices (board specific) */
 135         RCBA32(FD) = 0x17ee1fe1;
 136
 137         /* Enable HECI */
 138         RCBA32(FD2) &= ~0x2;
 139 }
 140
 141 void pch_enable_lpc(void)
 142 {
 143         /*
 144          * Enable:
 145          *  EC Decode Range PortA30/A20
 146          *  SuperIO Port2E/2F
 147          *  PS/2 Keyboard/Mouse Port60/64
 148          *  FDD Port3F0h-3F5h and Port3F7h
 149          */
 150         pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
 151                         CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
 152
 153         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
 154         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 155
 156         pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
 157
 158         /* Initialize SuperIO */
 159         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 160         it8728f_b75md3h_disable_reboot(SUPERIO_GPIO);
 161 }
 162
 163 const struct southbridge_usb_port mainboard_usb_ports[] = {
 164         { 1, 5, 0 },
 165         { 1, 5, 0 },
 166         { 1, 5, 1 },
 167         { 1, 5, 1 },
 168         { 1, 5, 2 },
 169         { 1, 5, 2 },
 170         { 1, 5, 3 },
 171         { 1, 5, 3 },
 172         { 1, 5, 4 },
 173         { 1, 5, 4 },
 174         { 1, 5, 6 },
 175         { 1, 5, 5 },
 176         { 1, 5, 5 },
 177         { 1, 5, 6 },
 178 };
 179
 180 void mainboard_get_spd(spd_raw_data *spd) {
 181         read_spd (&spd[0], 0x50);
 182         read_spd (&spd[1], 0x51);
 183         read_spd (&spd[2], 0x52);
 184         read_spd (&spd[3], 0x53);
 185 }
 186
 187 #if 0
 188 static void dmi_config(void)
 189 {
 190         DMIBAR32(0x0218) = 0x06aa0b0c;
 191         DMIBAR32(0x021c) = 0x0b0d0b0d;
 192         DMIBAR32(0x0300) = 0x0011028d;
 193         DMIBAR32(0x0304) = 0x002102cd;
 194         DMIBAR32(0x030c) = 0x007d004b;
 195         DMIBAR32(0x0310) = 0x007e004c;
 196         DMIBAR32(0x0318) = 0x002304ad;
 197         DMIBAR32(0x031c) = 0x003304ed;
 198         DMIBAR32(0x03b8) = 0x005c05a4;
 199         DMIBAR32(0x03bc) = 0x006c05e4;
 200         DMIBAR32(0x0530) = 0x41d3b000;
 201         DMIBAR32(0x0534) = 0x00019f80;
 202         DMIBAR32(0x0ba4) = 0x0000000d;
 203         DMIBAR32(0x0d80) = 0x1c9cfc0b;
 204         DMIBAR32(0x0e1c) = 0x20000000;
 205         DMIBAR32(0x0e2c) = 0x20000000;
 206 }
 207 #endif