src/mainboard/emulation/qemu-q35/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer@coreboot.org>
   5  * Copyright (C) 2010 Kevin O'Connor <kevin@koconnor.net>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <device/pci_ops.h>
  21 #include <pc80/keyboard.h>
  22 #include <arch/io.h>
  23 #include <console/console.h>
  24 #include <drivers/intel/gma/i915.h>
  25
  26 #define Q35_PAM0            0x90
  27
  28 static const unsigned char qemu_q35_irqs[] = {
  29         10, 10, 11, 11,
  30         10, 10, 11, 11,
  31 };
  32
  33 struct i915_gpu_controller_info gfx_controller_info = {
  34         .ndid = 3,
  35         .did = {
  36                 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005
  37         }
  38 };
  39
  40 const struct i915_gpu_controller_info *
  41 intel_gma_get_controller_info(void)
  42 {
  43         return &gfx_controller_info;
  44 }
  45
  46 static void qemu_nb_init(device_t dev)
  47 {
  48         /* Map memory at 0xc0000 - 0xfffff */
  49         int i;
  50         uint8_t v = pci_read_config8(dev, Q35_PAM0);
  51         v |= 0x30;
  52         pci_write_config8(dev, Q35_PAM0, v);
  53         pci_write_config8(dev, Q35_PAM0 + 1, 0x33);
  54         pci_write_config8(dev, Q35_PAM0 + 2, 0x33);
  55         pci_write_config8(dev, Q35_PAM0 + 3, 0x33);
  56         pci_write_config8(dev, Q35_PAM0 + 4, 0x33);
  57         pci_write_config8(dev, Q35_PAM0 + 5, 0x33);
  58         pci_write_config8(dev, Q35_PAM0 + 6, 0x33);
  59
  60         /* This sneaked in here, because Qemu does not
  61          * emulate a SuperIO chip
  62          */
  63         pc_keyboard_init();
  64
  65         /* setup IRQ routing for pci slots */
  66         for (i = 0; i < 25; i++)
  67                 pci_assign_irqs(0, i, qemu_q35_irqs + (i % 4));
  68         /* setup IRQ routing southbridge devices */
  69         for (i = 25; i < 32; i++)
  70                 pci_assign_irqs(0, i, qemu_q35_irqs);
  71 }
  72
  73 static void qemu_nb_read_resources(struct device *dev)
  74 {
  75         pci_dev_read_resources(dev);
  76
  77         /* reserve mmconfig */
  78         fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
  79                            IORESOURCE_RESERVE);
  80 }
  81
  82
  83 static struct device_operations nb_operations = {
  84         .read_resources   = qemu_nb_read_resources,
  85         .set_resources    = pci_dev_set_resources,
  86         .enable_resources = pci_dev_enable_resources,
  87         .init             = qemu_nb_init,
  88         .ops_pci          = 0,
  89 };
  90
  91 static const struct pci_driver nb_driver __pci_driver = {
  92         .ops = &nb_operations,
  93         .vendor = 0x8086,
  94         .device = 0x29c0,
  95 };