2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <cpu/x86/mtrr.h>
18 #include <cpu/x86/cache.h>
19 #include <cpu/x86/post_code.h>
22 #define CACHE_AS_RAM_SIZE 0x10000
23 #define CACHE_AS_RAM_BASE 0xd0000
25 #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
27 /* Save the BIST result. */
32 /* Clear the cache memory region. This will also fill up the cache */
33 movl $CACHE_AS_RAM_BASE, %esi
35 movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
36 // movl $0x23322332, %eax
41 /* Set up the stack pointer. */
42 movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
45 /* Restore the BIST result. */
52 /* Call romstage.c main function. */
58 post_code(POST_PREPARE_RAMSTAGE)
59 cld /* Clear direction flag. */
61 movl $CONFIG_RAMTOP, %esp
66 post_code(POST_DEAD_CODE)