src/mainboard/biostar/am1ml/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <device/pci_def.h>
  20 #include <device/pci_ids.h>
  21 #include <arch/acpi.h>
  22 #include <arch/io.h>
  23 #include <arch/stages.h>
  24 #include <device/pnp_def.h>
  25 #include <arch/cpu.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <console/console.h>
  28 #include <commonlib/loglevel.h>
  29 #include <cpu/amd/car.h>
  30 #include <northbridge/amd/agesa/agesawrapper.h>
  31 #include <cpu/x86/bist.h>
  32 #include <cpu/x86/lapic.h>
  33 #include <southbridge/amd/agesa/hudson/hudson.h>
  34 #include <cpu/amd/agesa/s3_resume.h>
  35 #include "cbmem.h"
  36 #include <superio/ite/common/ite.h>
  37 #include <superio/ite/it8728f/it8728f.h>
  38
  39
  40 #define ITE_CONFIG_REG_CC       0x02
  41 #define SERIAL_DEV      PNP_DEV(0x2e, IT8728F_SP1)
  42 #define GPIO_DEV        PNP_DEV(0x2e, IT8728F_GPIO)
  43 #define ENVC_DEV        PNP_DEV(0x2e, IT8728F_EC)
  44
  45 #define MMIO_NON_POSTED_START   0xfed00000
  46 #define MMIO_NON_POSTED_END     0xfedfffff
  47 #define SB_MMIO 0xFED80000
  48 #define SB_MMIO_MISC32(x)       *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
  49
  50
  51 static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
  52 {
  53         pnp_set_logical_device(dev);
  54         pnp_write_config(dev, reg, value);
  55 }
  56
  57 static void ite_enter_conf(pnp_devfn_t dev)
  58 {
  59         u16 port = dev >> 8;
  60
  61         outb(0x87, port);
  62         outb(0x01, port);
  63         outb(0x55, port);
  64         outb((port == 0x4e) ? 0xaa : 0x55, port);
  65 }
  66
  67 static void ite_exit_conf(pnp_devfn_t dev)
  68 {
  69         it_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
  70 }
  71
  72 static void ite_evc_conf(pnp_devfn_t dev)
  73 {
  74         ite_enter_conf(dev);
  75         it_sio_write(dev, 0xf1 , 0x40 );
  76         it_sio_write(dev, 0xf4 , 0x80 );
  77         it_sio_write(dev, 0xf5 , 0x00 );
  78         it_sio_write(dev, 0xf6 , 0xf0 );
  79         it_sio_write(dev, 0xf9 , 0x48 );
  80         it_sio_write(dev, 0xfa , 0x00 );
  81         it_sio_write(dev, 0xfb , 0x00 );
  82         ite_exit_conf(dev);
  83 }
  84
  85 static void ite_gpio_conf(pnp_devfn_t dev)
  86 {
  87         ite_enter_conf (dev);
  88         it_sio_write (dev, 0x25 , 0x80 );
  89         it_sio_write (dev, 0x26 , 0x07 );
  90         it_sio_write (dev, 0x28 , 0x81 );
  91         it_sio_write (dev, 0x2c , 0x06 );
  92         it_sio_write (dev, 0x72 , 0x00 );
  93         it_sio_write (dev, 0x73 , 0x00 );
  94         it_sio_write (dev, 0xb3 , 0x01 );
  95         it_sio_write (dev, 0xb8 , 0x00 );
  96         it_sio_write (dev, 0xc0 , 0x00 );
  97         it_sio_write (dev, 0xc3 , 0x00 );
  98         it_sio_write (dev, 0xc8 , 0x00 );
  99         it_sio_write (dev, 0xc9 , 0x07 );
 100         it_sio_write (dev, 0xcb , 0x01 );
 101         it_sio_write (dev, 0xf0 , 0x10 );
 102         it_sio_write (dev, 0xf4 , 0x27 );
 103         it_sio_write (dev, 0xf8 , 0x20 );
 104         it_sio_write (dev, 0xf9 , 0x01 );
 105         ite_exit_conf (dev);
 106 }
 107
 108
 109 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 110 {
 111         u32 val, t32;
 112         u8 byte;
 113         device_t dev;
 114         u32 *addr32;
 115
 116         /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 117          * LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
 118          * even though the register is not documented in the Kabini BKDG.
 119          * Otherwise the serial output is bad code.
 120          */
 121         outb(0xD2, 0xcd6);
 122         outb(0x00, 0xcd7);
 123
 124         amd_initmmio();
 125         /* Set LPC decode enables. */
 126         pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
 127         pci_write_config32(dev2, 0x44, 0xff03ffd5);
 128
 129         hudson_lpc_port80();
 130
 131         /* Enable the AcpiMmio space */
 132         outb(0x24, 0xcd6);
 133         outb(0x1, 0xcd7);
 134
 135         /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
 136         addr32 = (u32 *)0xfed80e28;
 137         t32 = *addr32;
 138         t32 &= 0xfff8ffff;
 139         *addr32 = t32;
 140
 141         /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
 142         addr32 = (u32 *)0xfed80e40;
 143         t32 = *addr32;
 144         t32 &= 0xffffbffb;
 145         *addr32 = t32;
 146
 147         if (!cpu_init_detectedx && boot_cpu()) {
 148                 /* enable SIO LPC decode */
 149                 dev = PCI_DEV(0, 0x14, 3);
 150                 byte = pci_read_config8(dev, 0x48);
 151                 byte |= 3;      /* 2e, 2f */
 152                 pci_write_config8(dev, 0x48, byte);
 153
 154                 /* enable serial decode */
 155                 byte = pci_read_config8(dev, 0x44);
 156                 byte |= (1 << 6);  /* 0x3f8 */
 157                 pci_write_config8(dev, 0x44, byte);
 158                 post_code(0x30);
 159                 post_code(0x31);
 160
 161                 /* run ite */
 162                 ite_kill_watchdog(GPIO_DEV);
 163                 ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 164
 165                 console_init();
 166         }
 167         printk(BIOS_DEBUG, "Console inited!\n");
 168         /* Halt if there was a built in self test failure */
 169         post_code(0x34);
 170         report_bist_failure(bist);
 171
 172
 173         /* Load MPB */
 174         val = cpuid_eax(1);
 175         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 176         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 177
 178         /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
 179         int i;
 180         for(i = 0; i < 200000; i++)
 181                 val = inb(0xcd6);
 182
 183         post_code(0x37);
 184         agesawrapper_amdinitreset();
 185         post_code(0x38);
 186         printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
 187
 188         post_code(0x39);
 189
 190         agesawrapper_amdinitearly();
 191         int s3resume = acpi_is_wakeup_s3();
 192         if (!s3resume) {
 193                 post_code(0x40);
 194                 agesawrapper_amdinitpost();
 195                 post_code(0x41);
 196                 agesawrapper_amdinitenv();
 197                 /* TODO: Disable cache is not ok. */
 198                 disable_cache_as_ram();
 199         } else { /* S3 detect */
 200                 printk(BIOS_INFO, "S3 detected\n");
 201
 202                 post_code(0x60);
 203                 agesawrapper_amdinitresume();
 204
 205                 amd_initcpuio();
 206                 agesawrapper_amds3laterestore();
 207
 208                 post_code(0x61);
 209                 prepare_for_resume();
 210         }
 211
 212         outb(0xEA, 0xCD6);
 213         outb(0x1, 0xcd7);
 214
 215         post_code(0x50);
 216         /* This functions configure SIO as it been done under vendor bios */
 217         printk(BIOS_DEBUG, "ITE CONFIG ENVC\n");
 218         ite_evc_conf(ENVC_DEV);
 219         printk(BIOS_DEBUG, "ITE CONFIG GPIO\n");
 220         ite_gpio_conf(GPIO_DEV);
 221         printk(BIOS_DEBUG, "ITE CONFIG DONE\n");
 222
 223         copy_and_run();
 224
 225         post_code(0x54);  /* Should never see this post code. */
 226 }