src/mainboard/asus/p3b-f/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <device/pci_def.h>
  19 #include <arch/io.h>
  20 #include <device/pnp_def.h>
  21 #include <stdlib.h>
  22 #include <console/console.h>
  23 #include <southbridge/intel/i82371eb/i82371eb.h>
  24 #include <northbridge/intel/i440bx/raminit.h>
  25 #include "drivers/pc80/udelay_io.c"
  26 #include <delay.h>
  27 #include <cpu/x86/bist.h>
  28 #include <superio/winbond/common/winbond.h>
  29 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
  30 #include <superio/winbond/w83977tf/w83977tf.h>
  31 #include <lib.h>
  32
  33 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
  34 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
  35
  36 int spd_read_byte(unsigned int device, unsigned int address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 /*
  42  * ASUS P3B-F specific SPD enable magic.
  43  *
  44  * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
  45  * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
  46  * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
  47  * will make RAM init fail.
  48  *
  49  * Tested values for PM I/O offset 0x37:
  50  * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
  51  * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
  52  * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
  53  *
  54  * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
  55  * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
  56  * control which SMBus/I2C offsets can be accessed.
  57  */
  58 static void enable_spd(void)
  59 {
  60         outb(0x6f, PM_IO_BASE + 0x37);
  61 }
  62
  63 /*
  64  * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
  65  * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
  66  */
  67 static void disable_spd(void)
  68 {
  69         outb(0x67, PM_IO_BASE + 0x37);
  70 }
  71
  72 #include <cpu/intel/romstage.h>
  73 void main(unsigned long bist)
  74 {
  75         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  76         console_init();
  77         report_bist_failure(bist);
  78
  79         enable_smbus();
  80         enable_pm();
  81
  82         enable_spd();
  83
  84         dump_spd_registers();
  85         sdram_set_registers();
  86         sdram_set_spd_registers();
  87         sdram_enable();
  88
  89         disable_spd();
  90 }