tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / asus / p2b-ds / mptable.c
blobef5ff8d1a02dff2849a6fe227aec10e24a86b562
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <arch/smp/mpspec.h>
19 #include <arch/ioapic.h>
20 #include <device/pci.h>
21 #include <string.h>
22 #include <stdint.h>
24 static void *smp_write_config_table(void *v)
26 int ioapic_id, ioapic_ver, isa_bus;
27 struct mp_config_table *mc;
29 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
31 mptable_init(mc, LOCAL_APIC_ADDR);
33 smp_write_processors(mc);
35 mptable_write_buses(mc, NULL, &isa_bus);
37 ioapic_id = 2;
38 ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
39 smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
41 /* Legacy Interrupts */
42 mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
44 /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
45 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13);
46 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13);
48 /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
49 mptable_lintsrc(mc, 0x1);
51 /* Compute the checksums. */
52 return mptable_finalize(mc);
55 unsigned long write_smp_table(unsigned long addr)
57 void *v;
58 v = smp_write_floating_table(addr, 0);
59 return (unsigned long)smp_write_config_table(v);