src/mainboard/asus/m4a785-m/get_bus_conf.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/pci.h>
  18 #include <device/pci_ids.h>
  19 #include <string.h>
  20 #include <stdint.h>
  21 #include <stdlib.h>
  22 #include <cpu/amd/multicore.h>
  23
  24 #include <cpu/amd/amdfam10_sysconf.h>
  25
  26 /* Global variables for MB layouts and these will be shared by irqtable mptable
  27 * and acpi_tables busnum is default.
  28 */
  29 u8 bus_rs780[11];
  30 u8 bus_sb700[2];
  31 u32 apicid_sb700;
  32
  33 /*
  34 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
  35 * You may need to preset pci1234 for HTIO board,
  36 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
  37 */
  38 u32 pci1234x[] = {
  39         0x0000ff0,
  40 };
  41
  42 /*
  43 * HT Chain device num, actually it is unit id base of every ht device in chain,
  44 * assume every chain only have 4 ht device at most
  45 */
  46 u32 hcdnx[] = {
  47         0x20202020,
  48 };
  49
  50 u32 sbdn_rs780;
  51 u32 sbdn_sb700;
  52
  53 extern void get_pci1234(void);
  54
  55 static u32 get_bus_conf_done = 0;
  56
  57 void get_bus_conf(void)
  58 {
  59         u32 apicid_base;
  60         device_t dev;
  61         int i;
  62
  63         if (get_bus_conf_done == 1)
  64                 return;         /* do it only once */
  65         get_bus_conf_done = 1;
  66
  67         sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
  68         for (i = 0; i < sysconf.hc_possible_num; i++) {
  69                 sysconf.pci1234[i] = pci1234x[i];
  70                 sysconf.hcdn[i] = hcdnx[i];
  71         }
  72
  73         get_pci1234();
  74
  75         sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
  76         sbdn_rs780 = sysconf.sbdn;
  77         sbdn_sb700 = 0;
  78
  79         for (i = 0; i < 2; i++) {
  80                 bus_sb700[i] = 0;
  81         }
  82         for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
  83                 bus_rs780[i] = 0;
  84         }
  85
  86         bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
  87         bus_sb700[0] = bus_rs780[0];
  88
  89         /* sb700 */
  90         dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
  91         if (dev) {
  92                 bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
  93         }
  94
  95         /* rs780 */
  96         for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
  97                 dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
  98                 if (dev) {
  99                         bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 100                 }
 101         }
 102
 103         /* I/O APICs:   APIC ID Version State   Address */
 104         if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
 105                 apicid_base = get_apicid_base(1);
 106         else
 107                 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 108         apicid_sb700 = apicid_base + 0;
 109 }