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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / asus / m4a78-em / resourcemap.c
blob95d009ac1e878dde06f90e317844e715158b0d42
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16
17
18 static void setup_mb_resource_map(void)
19 {
20 static const unsigned int register_values[] = {
21 /* Careful set limit registers before base registers which contain the enables */
22 /* DRAM Limit i Registers
23 * F1:0x44 i = 0
24 * F1:0x4C i = 1
25 * F1:0x54 i = 2
26 * F1:0x5C i = 3
27 * F1:0x64 i = 4
28 * F1:0x6C i = 5
29 * F1:0x74 i = 6
30 * F1:0x7C i = 7
31 * [ 2: 0] Destination Node ID
32 * 000 = Node 0
33 * 001 = Node 1
34 * 010 = Node 2
35 * 011 = Node 3
36 * 100 = Node 4
37 * 101 = Node 5
38 * 110 = Node 6
39 * 111 = Node 7
40 * [ 7: 3] Reserved
41 * [10: 8] Interleave select
42 * specifies the values of A[14:12] to use with interleave enable.
43 * [15:11] Reserved
44 * [31:16] DRAM Limit Address i Bits 39-24
45 * This field defines the upper address bits of a 40 bit address
46 * that define the end of the DRAM region.
47 */
48 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
49 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
50 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
51 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
52 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
53 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
54 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
55 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
56 /* DRAM Base i Registers
57 * F1:0x40 i = 0
58 * F1:0x48 i = 1
59 * F1:0x50 i = 2
60 * F1:0x58 i = 3
61 * F1:0x60 i = 4
62 * F1:0x68 i = 5
63 * F1:0x70 i = 6
64 * F1:0x78 i = 7
65 * [ 0: 0] Read Enable
66 * 0 = Reads Disabled
67 * 1 = Reads Enabled
68 * [ 1: 1] Write Enable
69 * 0 = Writes Disabled
70 * 1 = Writes Enabled
71 * [ 7: 2] Reserved
72 * [10: 8] Interleave Enable
73 * 000 = No interleave
74 * 001 = Interleave on A[12] (2 nodes)
75 * 010 = reserved
76 * 011 = Interleave on A[12] and A[14] (4 nodes)
77 * 100 = reserved
78 * 101 = reserved
79 * 110 = reserved
80 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
81 * [15:11] Reserved
82 * [13:16] DRAM Base Address i Bits 39-24
83 * This field defines the upper address bits of a 40-bit address
84 * that define the start of the DRAM region.
85 */
86 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
87 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
88 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
89 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
90 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
91 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
92 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
93 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
94
95 /* Memory-Mapped I/O Limit i Registers
96 * F1:0x84 i = 0
97 * F1:0x8C i = 1
98 * F1:0x94 i = 2
99 * F1:0x9C i = 3
100 * F1:0xA4 i = 4
101 * F1:0xAC i = 5
102 * F1:0xB4 i = 6
103 * F1:0xBC i = 7
104 * [ 2: 0] Destination Node ID
105 * 000 = Node 0
106 * 001 = Node 1
107 * 010 = Node 2
108 * 011 = Node 3
109 * 100 = Node 4
110 * 101 = Node 5
111 * 110 = Node 6
112 * 111 = Node 7
113 * [ 3: 3] Reserved
114 * [ 5: 4] Destination Link ID
115 * 00 = Link 0
116 * 01 = Link 1
117 * 10 = Link 2
118 * 11 = Reserved
119 * [ 6: 6] Reserved
120 * [ 7: 7] Non-Posted
121 * 0 = CPU writes may be posted
122 * 1 = CPU writes must be non-posted
123 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
124 * This field defines the upp adddress bits of a 40-bit address that
125 * defines the end of a memory-mapped I/O region n
126 */
127 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
128 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
129 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
130 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
131 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
132 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
133 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
134 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
135
136 /* Memory-Mapped I/O Base i Registers
137 * F1:0x80 i = 0
138 * F1:0x88 i = 1
139 * F1:0x90 i = 2
140 * F1:0x98 i = 3
141 * F1:0xA0 i = 4
142 * F1:0xA8 i = 5
143 * F1:0xB0 i = 6
144 * F1:0xB8 i = 7
145 * [ 0: 0] Read Enable
146 * 0 = Reads disabled
147 * 1 = Reads Enabled
148 * [ 1: 1] Write Enable
149 * 0 = Writes disabled
150 * 1 = Writes Enabled
151 * [ 2: 2] Cpu Disable
152 * 0 = Cpu can use this I/O range
153 * 1 = Cpu requests do not use this I/O range
154 * [ 3: 3] Lock
155 * 0 = base/limit registers i are read/write
156 * 1 = base/limit registers i are read-only
157 * [ 7: 4] Reserved
158 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
159 * This field defines the upper address bits of a 40bit address
160 * that defines the start of memory-mapped I/O region i
161 */
162 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
163 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
164 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
165 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
166 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
167 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
168 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
169 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
170
171 /* PCI I/O Limit i Registers
172 * F1:0xC4 i = 0
173 * F1:0xCC i = 1
174 * F1:0xD4 i = 2
175 * F1:0xDC i = 3
176 * [ 2: 0] Destination Node ID
177 * 000 = Node 0
178 * 001 = Node 1
179 * 010 = Node 2
180 * 011 = Node 3
181 * 100 = Node 4
182 * 101 = Node 5
183 * 110 = Node 6
184 * 111 = Node 7
185 * [ 3: 3] Reserved
186 * [ 5: 4] Destination Link ID
187 * 00 = Link 0
188 * 01 = Link 1
189 * 10 = Link 2
190 * 11 = reserved
191 * [11: 6] Reserved
192 * [24:12] PCI I/O Limit Address i
193 * This field defines the end of PCI I/O region n
194 * [31:25] Reserved
195 */
196 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
197 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
198 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
199 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
200
201 /* PCI I/O Base i Registers
202 * F1:0xC0 i = 0
203 * F1:0xC8 i = 1
204 * F1:0xD0 i = 2
205 * F1:0xD8 i = 3
206 * [ 0: 0] Read Enable
207 * 0 = Reads Disabled
208 * 1 = Reads Enabled
209 * [ 1: 1] Write Enable
210 * 0 = Writes Disabled
211 * 1 = Writes Enabled
212 * [ 3: 2] Reserved
213 * [ 4: 4] VGA Enable
214 * 0 = VGA matches Disabled
215 * 1 = matches all address < 64K and where A[9:0] is in the
216 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
217 * [ 5: 5] ISA Enable
218 * 0 = ISA matches Disabled
219 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
220 * from matching agains this base/limit pair
221 * [11: 6] Reserved
222 * [24:12] PCI I/O Base i
223 * This field defines the start of PCI I/O region n
224 * [31:25] Reserved
225 */
226 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
227 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
228 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
229 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
230
231 /* Config Base and Limit i Registers
232 * F1:0xE0 i = 0
233 * F1:0xE4 i = 1
234 * F1:0xE8 i = 2
235 * F1:0xEC i = 3
236 * [ 0: 0] Read Enable
237 * 0 = Reads Disabled
238 * 1 = Reads Enabled
239 * [ 1: 1] Write Enable
240 * 0 = Writes Disabled
241 * 1 = Writes Enabled
242 * [ 2: 2] Device Number Compare Enable
243 * 0 = The ranges are based on bus number
244 * 1 = The ranges are ranges of devices on bus 0
245 * [ 3: 3] Reserved
246 * [ 6: 4] Destination Node
247 * 000 = Node 0
248 * 001 = Node 1
249 * 010 = Node 2
250 * 011 = Node 3
251 * 100 = Node 4
252 * 101 = Node 5
253 * 110 = Node 6
254 * 111 = Node 7
255 * [ 7: 7] Reserved
256 * [ 9: 8] Destination Link
257 * 00 = Link 0
258 * 01 = Link 1
259 * 10 = Link 2
260 * 11 - Reserved
261 * [15:10] Reserved
262 * [23:16] Bus Number Base i
263 * This field defines the lowest bus number in configuration region i
264 * [31:24] Bus Number Limit i
265 * This field defines the highest bus number in configuration regin i
266 */
267 // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
268 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
269 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
270 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
271 };
272
273 int max;
274 max = ARRAY_SIZE(register_values);
275 setup_resource_map(register_values, max);
276 }
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