2 * This file is part of the coreboot project.
4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
6 * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
7 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
23 /* SuperIO control port */
26 /* SuperIO control map */
27 OperationRegion (SPIM, SystemIO, SPIO, 0x02)
28 Field (SPIM, ByteAcc, NoLock, Preserve) {
33 /* SuperIO control registers */
34 IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
36 CR07, 8, /* Logical device number */
38 CR2C, 8, /* GPIO3 multiplexed pin selection */
40 CR30, 8, /* Logical device activation control register */
42 CRE0, 8, /* Wake control register */
44 CRE6, 8, /* Mouse wake event configuration register */
46 CRF1, 8, /* GPIO3 data register */
48 CRF3, 8, /* SUSLED mode register */
50 CRF6, 8, /* SMI/PME event generation control register */
52 CRF9, 8, /* ACPI PME configuration register */
55 /* Southbridge control ports */
56 /* Both are offsets from PM base address (0x2000) */
57 Name (SBC1, 0x2090) /* Offset 0x90 */
58 Name (SBC2, 0x2400) /* Offset 0x400 */
60 /* Southbridge control maps */
61 OperationRegion (SBM1, SystemIO, SBC1, 0x10)
62 Field (SBM1, ByteAcc, NoLock, Preserve) {
71 OperationRegion (SBM2, SystemIO, SBC2, 0x08)
72 Field (SBM2, ByteAcc, NoLock, Preserve) {
79 /* Wake status package */
80 Name(WKST,Package(){Zero, Zero})
83 * \_WAK System Wake method
86 * Arg0=The value of the sleeping state S1=1, S2=2
89 * Return package of 2 DWords
91 * 0x00000000 wake succeeded
92 * 0x00000001 Wake was signaled but failed due to lack of power
93 * 0x00000002 Wake was signaled but failed due to thermal condition
94 * Dword 2 - Power Supply state
95 * if non-zero the effective S-state the power supply entered
99 /* Access SuperIO GPIO3/GPIO4 device */
104 /* Set GPIO3 pin 64 (power LED) to GP37 mode */
105 And(CR2C, 0xF3, Local0)
106 Or(Local0, 0x04, CR2C)
108 /* Set power LED to steady on */
111 /* Restore default SuperIO access */
114 /* Configure SuperIO for wake */
115 /* Access SuperIO ACPI device */
120 if (LEqual(Arg0, One)) /* Resuming from power state S1 */
122 /* Set power management to SMI mode and disable SMI events */
123 And(CRF9, 0xFA, CRF9)
125 /* Deactivate the ACPI device */
128 /* Disable PS/2 SMI/PME events */
129 And(CRF6, 0xCF, CRF6)
131 if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
133 /* Disable PS/2 wake */
134 And(CRE0, 0x1D, CRE0)
135 And(CRE6, 0x7F, CRE6)
138 /* Restore default SuperIO access */
141 /* Configure southbridge for wake */
147 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
150 } /* End Method(\_WAK) */
153 * \_PTS - Prepare to Sleep method
156 * Arg0=The value of the sleeping state S1=1, S2=2, etc
161 * The _PTS control method is executed at the beginning of the sleep process
162 * for S1-S5. The sleeping value is passed to the _PTS control method. This
163 * control method may be executed a relatively long time before entering the
164 * sleep state and the OS may abort the operation without notification to
165 * the ACPI driver. This method cannot modify the configuration or power
166 * state of any device in the system.
170 if (LEqual(Arg0, One)) /* Power state S1 requested */
172 /* Access SuperIO GPIO3/GPIO4 device */
177 /* Set GPIO3 pin 64 (power LED) to SUSLED mode */
178 And(CR2C, 0xF3, CR2C)
180 /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */
183 /* Restore default SuperIO access */
187 /* Configure SuperIO for sleep */
188 /* Access SuperIO ACPI device */
193 /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
194 And(CRE0, 0x1F, CRE0)
196 if (LEqual(Arg0, One)) /* Power state S1 requested */
198 /* Set power management to PME mode and enable PME events */
201 /* Activate the ACPI device */
204 /* Enable PS/2 keyboard SMI/PME events */
205 And(CRF6, 0xEF, CRF6)
207 /* Enable PS/2 keyboard wake */
210 /* Enable PS/2 mouse SMI/PME events */
211 And(CRF6, 0xDF, CRF6)
213 /* Enable PS/2 mouse wake */
217 /* Enable PS/2 keyboard wake on any keypress */
220 /* Enable PS/2 mouse wake on any click */
225 /* Restore default SuperIO access */
228 /* Configure southbridge for sleep */
232 /* On older chips, clear PciExpWakeDisEn */
233 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
238 /* Clear wake status structure. */
239 Store(0, Index(WKST,0))
240 Store(0, Index(WKST,1))
241 } /* End Method(\_PTS) */