src/mainboard/asus/k8v-x/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2006 MSI
   7  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
   8  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 unsigned int get_sbdn(unsigned bus);
  22
  23 #include <stdint.h>
  24 #include <string.h>
  25 #include <device/pci_def.h>
  26 #include <arch/io.h>
  27 #include <device/pnp_def.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <pc80/mc146818rtc.h>
  30 #include <console/console.h>
  31 #include <cpu/amd/model_fxx_rev.h>
  32 #include <halt.h>
  33 #include <northbridge/amd/amdk8/raminit.h>
  34 #include <delay.h>
  35 #include <cpu/x86/lapic.h>
  36 #include "northbridge/amd/amdk8/reset_test.c"
  37 #include "northbridge/amd/amdk8/early_ht.c"
  38 #include <superio/winbond/common/winbond.h>
  39 #include <superio/winbond/w83697hf/w83697hf.h>
  40 #include "southbridge/via/vt8237r/early_smbus.c"
  41 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
  42 #include <cpu/x86/bist.h>
  43 #include "northbridge/amd/amdk8/setup_resource_map.c"
  44 #include <spd.h>
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
  47
  48 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  49 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 #include <reset.h>
  57 void soft_reset(void)
  58 {
  59         uint8_t tmp;
  60
  61         set_bios_reset();
  62         printk(BIOS_DEBUG, "soft reset\n");
  63
  64         /* PCI reset */
  65         tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
  66         tmp |= 0x01;
  67         pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
  68
  69         halt();
  70 }
  71
  72 #include "southbridge/via/k8t890/early_car.c"
  73 #include <northbridge/amd/amdk8/amdk8.h>
  74 #include "northbridge/amd/amdk8/incoherent_ht.c"
  75 #include "northbridge/amd/amdk8/coherent_ht.c"
  76 #include "northbridge/amd/amdk8/raminit.c"
  77 #include "lib/generic_sdram.c"
  78 #include "cpu/amd/dualcore/dualcore.c"
  79 #include "cpu/amd/model_fxx/init_cpus.c"
  80 #include "cpu/amd/model_fxx/fidvid.c"
  81 #include "northbridge/amd/amdk8/resourcemap.c"
  82
  83 unsigned int get_sbdn(unsigned bus)
  84 {
  85         device_t dev;
  86
  87         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  88                                         PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
  89         return (dev >> 15) & 0x1f;
  90 }
  91
  92 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  93 {
  94         static const uint16_t spd_addr[] = {
  95                 // Node 0
  96                 DIMM0, DIMM1, DIMM2, 0,
  97                 0, 0, 0, 0,
  98                 // Node 1
  99                 0, 0, 0, 0,
 100                 0, 0, 0, 0,
 101         };
 102         unsigned bsp_apicid = 0;
 103         int needs_reset = 0;
 104         struct sys_info *sysinfo = &sysinfo_car;
 105
 106         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 107         console_init();
 108         enable_rom_decode();
 109
 110         printk(BIOS_INFO, "now booting... fallback\n");
 111
 112         /* Is this a CPU only reset? Or is this a secondary CPU? */
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0. */
 115                 /* Allow the HT devices to be found. */
 116                 enumerate_ht_chain();
 117         }
 118
 119         printk(BIOS_INFO, "now booting... real_main\n");
 120
 121         if (bist == 0)
 122                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 123
 124         /* Halt if there was a built in self test failure. */
 125         report_bist_failure(bist);
 126
 127         setup_default_resource_map();
 128         setup_coherent_ht_domain();
 129         wait_all_core0_started();
 130
 131         printk(BIOS_INFO, "now booting... Core0 started\n");
 132
 133 #if CONFIG_LOGICAL_CPUS
 134         /* It is said that we should start core1 after all core0 launched. */
 135         start_other_cores();
 136         wait_all_other_cores_started(bsp_apicid);
 137 #endif
 138         init_timer();
 139         ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 140
 141         needs_reset = optimize_link_coherent_ht();
 142         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 143         needs_reset |= k8t890_early_setup_ht();
 144
 145         if (needs_reset) {
 146                 printk(BIOS_DEBUG, "ht reset -\n");
 147                 soft_reset();
 148         }
 149
 150         /* the HT settings needs to be OK, because link freq change may cause HT disconnect */
 151         vt8237_sb_enable_fid_vid();
 152         enable_fid_change();
 153         init_fidvid_bsp(bsp_apicid);
 154
 155         /* Stop the APs so we can start them later in init. */
 156         allow_all_aps_stop(bsp_apicid);
 157
 158         /* It's the time to set ctrl now. */
 159         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 160
 161         enable_smbus();
 162
 163         /* this seems to be some GPIO on the SMBus--in any case, setting these
 164          * two bits reduces the pullup impedance of the bus lines and is required
 165          * in order to be able to read SPD info */
 166         smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
 167         smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
 168
 169         unsigned char mask;
 170
 171         mask = 0;
 172 //      mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
 173 //      mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
 174         smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
 175         smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
 176
 177         mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
 178         mask = 3 - (mask - 25);
 179         smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
 180         smbus_write_byte(0x4a, 0x03, 0x04 | mask);
 181
 182         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 183         post_cache_as_ram();
 184 }