src/mainboard/asus/f2a85-m_le/buildOpts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /**
  17  * @file
  18  *
  19  * AMD User options selection for a Brazos platform solution system
  20  *
  21  * This file is placed in the user's platform directory and contains the
  22  * build option selections desired for that platform.
  23  *
  24  * For Information about this file, see @ref platforminstall.
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29
  30 #include <vendorcode/amd/agesa/f15tn/AGESA.h>
  31
  32 /*  Include the files that instantiate the configuration definitions.  */
  33 #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
  34 #include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
  35 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
  36 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
  37 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
  38 /* the next two headers depend on heapManager.h */
  39 #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
  40 #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
  41 /* These tables are optional and may be used to adjust memory timing settings */
  42 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
  43 #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
  44
  45 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
  46
  47 /*  Select the cpu family.  */
  48 #define INSTALL_FAMILY_10_SUPPORT FALSE
  49 #define INSTALL_FAMILY_12_SUPPORT FALSE
  50 #define INSTALL_FAMILY_14_SUPPORT FALSE
  51 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
  52
  53 /*  Select the cpu socket type.  */
  54 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
  55 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
  56 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
  57 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
  58 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
  59 #define INSTALL_FS1_SOCKET_SUPPORT  FALSE
  60 #define INSTALL_FM1_SOCKET_SUPPORT  FALSE
  61 #define INSTALL_FP2_SOCKET_SUPPORT  FALSE
  62 #define INSTALL_FT1_SOCKET_SUPPORT  FALSE
  63 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
  64
  65 #define INSTALL_FM2_SOCKET_SUPPORT  TRUE
  66
  67 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
  68 #define BLDOPT_REMOVE_SODIMMS_SUPPORT          TRUE
  69 #define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
  70 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
  71 #define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
  72 //#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
  73 //#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
  74 #define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
  75 #define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
  76 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
  77 //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
  78 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
  79 //#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
  80 #define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
  81 #define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
  82 #define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
  83 #define BLDOPT_REMOVE_CRAT                      TRUE
  84 #define BLDOPT_REMOVE_DMI                      TRUE
  85 //#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
  86 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
  87 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
  88 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
  89 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
  90 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
  91
  92 //This element selects whether P-States should be forced to be independent,
  93 // as reported by the ACPI _PSD object. For single-link processors,
  94 // setting TRUE for OS to support this feature.
  95
  96 //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
  97
  98 #define BLDCFG_PCI_MMIO_BASE    CONFIG_MMCONF_BASE_ADDRESS
  99 #define BLDCFG_PCI_MMIO_SIZE    CONFIG_MMCONF_BUS_NUMBER
 100 /* Build configuration values here.
 101  */
 102 #define BLDCFG_VRM_CURRENT_LIMIT                 90000
 103 #define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
 104 #define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          0
 105 #define BLDCFG_PLAT_NUM_IO_APICS                 3
 106 #define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
 107 #define BLDCFG_MEM_INIT_PSTATE                   0
 108
 109 #define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
 110
 111 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY
 112 #define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
 113 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
 114 #define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
 115 #define BLDCFG_MEMORY_RDIMM_CAPABLE               FALSE
 116 #define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
 117 #define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
 118 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
 119 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
 120 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
 121 #define BLDCFG_MEMORY_POWER_DOWN                  TRUE
 122 #define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
 123 #define BLDCFG_ONLINE_SPARE                       FALSE
 124 #define BLDCFG_BANK_SWIZZLE                       TRUE
 125 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
 126 #define BLDCFG_MEMORY_CLOCK_SELECT                DDR1600_FREQUENCY
 127 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 128 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 129 #define BLDCFG_USE_BURST_MODE                     FALSE
 130 #define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
 131 #define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
 132 #define BLDCFG_ECC_REDIRECTION                    FALSE
 133 #define BLDCFG_SCRUB_DRAM_RATE                    0
 134 #define BLDCFG_SCRUB_L2_RATE                      0
 135 #define BLDCFG_SCRUB_L3_RATE                      0
 136 #define BLDCFG_SCRUB_IC_RATE                      0
 137 #define BLDCFG_SCRUB_DC_RATE                      0
 138 #define BLDCFG_ECC_SYMBOL_SIZE                    4
 139 #define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
 140 #define BLDCFG_ECC_SYNC_FLOOD                     FALSE
 141 #define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
 142 #define BLDCFG_1GB_ALIGN                          FALSE
 143 #define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
 144 #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM        36            // PCIE Spread Spectrum default value 0.36%
 145 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770
 146
 147 #define BLDOPT_REMOVE_ALIB                    FALSE
 148 #define BLDCFG_PLATFORM_CPB_MODE                  CpbModeDisabled
 149 #define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
 150 #define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
 151 #define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
 152
 153 #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         200
 154 #define BLDCFG_CFG_ABM_SUPPORT                    0
 155
 156 //#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
 157
 158 // Specify the default values for the VRM controlling the VDDNB plane.
 159 // If not specified, the values used for the core VRM will be applied
 160 //#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Trinity
 161 //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
 162 //#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime
 163 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Trinity
 164 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Trinity
 165 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Trinity
 166
 167 #define BLDCFG_VRM_NB_CURRENT_LIMIT               60000
 168
 169 #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON        3
 170 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL        3
 171
 172 #if CONFIG_GFXUMA
 173 #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
 174 #define BLDCFG_UMA_ALLOCATION_MODE                UMA_SPECIFIED
 175 //#define BLDCFG_UMA_ALLOCATION_SIZE              0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
 176 #define BLDCFG_UMA_ALLOCATION_SIZE                0x2000//512M
 177 #define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
 178 #endif
 179
 180 #define BLDCFG_IOMMU_SUPPORT    FALSE
 181
 182 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE
 183 //#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
 184 //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
 185 //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
 186
 187 /*  Process the options...
 188  * This file include MUST occur AFTER the user option selection settings
 189  */
 190 #define AGESA_ENTRY_INIT_RESET                    TRUE
 191 #define AGESA_ENTRY_INIT_RECOVERY                 FALSE
 192 #define AGESA_ENTRY_INIT_EARLY                    TRUE
 193 #define AGESA_ENTRY_INIT_POST                     TRUE
 194 #define AGESA_ENTRY_INIT_ENV                      TRUE
 195 #define AGESA_ENTRY_INIT_MID                      TRUE
 196 #define AGESA_ENTRY_INIT_LATE                     TRUE
 197 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 198 #define AGESA_ENTRY_INIT_RESUME                   TRUE //TRUE
 199 #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
 200 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 201 /*
 202  * Customized OEM build configurations for FCH component
 203  */
 204 // #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
 205 // #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
 206 // #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
 207 // #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
 208 // #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
 209 // #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
 210 // #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
 211 // #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
 212 // #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
 213 // #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
 214 // #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
 215 // #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
 216 // #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
 217 // #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
 218 // #define BLDCFG_AZALIA_SSID                    0x780D1022
 219 // #define BLDCFG_SMBUS_SSID                     0x780B1022
 220 // #define BLDCFG_IDE_SSID                       0x780C1022
 221 // #define BLDCFG_SATA_AHCI_SSID                 0x78011022
 222 // #define BLDCFG_SATA_IDE_SSID                  0x78001022
 223 // #define BLDCFG_SATA_RAID5_SSID                0x78031022
 224 // #define BLDCFG_SATA_RAID_SSID                 0x78021022
 225 // #define BLDCFG_EHCI_SSID                      0x78081022
 226 // #define BLDCFG_OHCI_SSID                      0x78071022
 227 // #define BLDCFG_LPC_SSID                       0x780E1022
 228 // #define BLDCFG_SD_SSID                        0x78061022
 229 // #define BLDCFG_XHCI_SSID                      0x78121022
 230 // #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
 231 // #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
 232 // #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
 233 // #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
 234 // #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
 235 // #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
 236 // #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
 237 // #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
 238 // #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
 239 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
 240 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
 241
 242 CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
 243 {
 244   { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
 245   { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
 246   { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
 247   { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
 248   { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
 249   { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
 250   { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
 251   { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
 252   { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
 253   { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
 254   { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
 255   { CPU_LIST_TERMINAL }
 256 };
 257
 258 #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
 259
 260                   // This is the delivery package title, "BrazosPI"
 261                   // This string MUST be exactly 8 characters long
 262 #define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 263
 264                   // This is the release version number of the AGESA component
 265                   // This string MUST be exactly 12 characters long
 266 #define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
 267
 268 /* MEMORY_BUS_SPEED */
 269 #define DDR400_FREQUENCY   200     ///< DDR 400
 270 #define DDR533_FREQUENCY   266     ///< DDR 533
 271 #define DDR667_FREQUENCY   333     ///< DDR 667
 272 #define DDR800_FREQUENCY   400     ///< DDR 800
 273 #define DDR1066_FREQUENCY   533    ///< DDR 1066
 274 #define DDR1333_FREQUENCY   667    ///< DDR 1333
 275 #define DDR1600_FREQUENCY   800    ///< DDR 1600
 276 #define DDR1866_FREQUENCY   933    ///< DDR 1866
 277 #define DDR2100_FREQUENCY   1050   ///< DDR 2100
 278 #define DDR2133_FREQUENCY   1066   ///< DDR 2133
 279 #define DDR2400_FREQUENCY   1200   ///< DDR 2400
 280 #define UNSUPPORTED_DDR_FREQUENCY               1201 ///< Highest limit of DDR frequency
 281
 282 /* QUANDRANK_TYPE*/
 283 #define QUADRANK_REGISTERED                             0 ///< Quadrank registered DIMM
 284 #define QUADRANK_UNBUFFERED                             1 ///< Quadrank unbuffered DIMM
 285
 286 /* USER_MEMORY_TIMING_MODE */
 287 #define TIMING_MODE_AUTO                                0 ///< Use best rate possible
 288 #define TIMING_MODE_LIMITED                             1 ///< Set user top limit
 289 #define TIMING_MODE_SPECIFIC                    2 ///< Set user specified speed
 290
 291 /* POWER_DOWN_MODE */
 292 #define POWER_DOWN_BY_CHANNEL                   0 ///< Channel power down mode
 293 #define POWER_DOWN_BY_CHIP_SELECT               1 ///< Chip select power down mode
 294
 295 /*
 296  * Agesa optional capabilities selection.
 297  * Uncomment and mark FALSE those features you wish to include in the build.
 298  * Comment out or mark TRUE those features you want to REMOVE from the build.
 299  */
 300
 301 #define DFLT_SMBUS0_BASE_ADDRESS            0xB00
 302 #define DFLT_SMBUS1_BASE_ADDRESS            0xB20
 303 /* The AGESA likes to enable 512 bytes region on this base for LPC bus */
 304 #define DFLT_SIO_PME_BASE_ADDRESS           0xE00
 305 #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
 306 #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
 307 #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
 308 #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
 309 #define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
 310 #define DFLT_SPI_BASE_ADDRESS               0xFEC10000
 311 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
 312 #define DFLT_HPET_BASE_ADDRESS              0xFED00000
 313 #define DFLT_SMI_CMD_PORT                   0xB0
 314 #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
 315 #define DFLT_GEC_BASE_ADDRESS               0xFED61000
 316 #define DFLT_AZALIA_SSID                    0x780D1022
 317 #define DFLT_SMBUS_SSID                     0x780B1022
 318 #define DFLT_IDE_SSID                       0x780C1022
 319 #define DFLT_SATA_AHCI_SSID                 0x78011022
 320 #define DFLT_SATA_IDE_SSID                  0x78001022
 321 #define DFLT_SATA_RAID5_SSID                0x78031022
 322 #define DFLT_SATA_RAID_SSID                 0x78021022
 323 #define DFLT_EHCI_SSID                      0x78081022
 324 #define DFLT_OHCI_SSID                      0x78071022
 325 #define DFLT_LPC_SSID                       0x780E1022
 326 #define DFLT_SD_SSID                        0x78061022
 327 #define DFLT_XHCI_SSID                      0x78121022
 328 #define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
 329 #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
 330 #define DFLT_FCH_GPP_LINK_CONFIG            PortA1B1C1D1
 331 #define DFLT_FCH_GPP_PORT0_PRESENT          TRUE
 332 #define DFLT_FCH_GPP_PORT1_PRESENT          TRUE
 333 #define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
 334 #define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
 335 #define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
 336 #define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
 337 #define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
 338 #define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
 339 //#define BLDCFG_IR_PIN_CONTROL 0x33
 340 //#define FCH_NO_XHCI_SUPPORT                   FALSE
 341 GPIO_CONTROL   f2a85_m_gpio[] = {
 342 //      {183, Function1, PullUpB},
 343         {-1}
 344 };
 345 #define BLDCFG_FCH_GPIO_CONTROL_LIST           (&f2a85_m_gpio[0])
 346
 347 // The following definitions specify the default values for various parameters in which there are
 348 // no clearly defined defaults to be used in the common file.  The values below are based on product
 349 // and BKDG content, please consult the AGESA Memory team for consultation.
 350 #define DFLT_SCRUB_DRAM_RATE            (0)
 351 #define DFLT_SCRUB_L2_RATE              (0)
 352 #define DFLT_SCRUB_L3_RATE              (0)
 353 #define DFLT_SCRUB_IC_RATE              (0)
 354 #define DFLT_SCRUB_DC_RATE              (0)
 355 #define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
 356 #define DFLT_VRM_SLEW_RATE              (5000)
 357
 358 /* Moving this include up will break AGESA. */
 359 #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
 360
 361 /*----------------------------------------------------------------------------------------
 362  *                        CUSTOMER OVERIDES MEMORY TABLE
 363  *----------------------------------------------------------------------------------------
 364  */
 365
 366 /*
 367  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 368  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 369  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 370  *  use its default conservative settings.
 371  */
 372 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 373   //
 374   // The following macros are supported (use comma to separate macros):
 375   //
 376   // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
 377   //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
 378   //      AGESA will base on this value to disable unused MemClk to save power.
 379   //      Example:
 380   //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
 381   //           Bit AM3/S1g3 pin name
 382   //           0   M[B,A]_CLK_H/L[0]
 383   //           1   M[B,A]_CLK_H/L[1]
 384   //           2   M[B,A]_CLK_H/L[2]
 385   //           3   M[B,A]_CLK_H/L[3]
 386   //           4   M[B,A]_CLK_H/L[4]
 387   //           5   M[B,A]_CLK_H/L[5]
 388   //           6   M[B,A]_CLK_H/L[6]
 389   //           7   M[B,A]_CLK_H/L[7]
 390   //      And platform has the following routing:
 391   //           CS0   M[B,A]_CLK_H/L[4]
 392   //           CS1   M[B,A]_CLK_H/L[2]
 393   //           CS2   M[B,A]_CLK_H/L[3]
 394   //           CS3   M[B,A]_CLK_H/L[5]
 395   //      Then platform can specify the following macro:
 396   //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
 397   //
 398   // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
 399   //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
 400   //      AGESA will base on this value to tristate unused CKE to save power.
 401   //
 402   // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
 403   //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
 404   //      AGESA will base on this value to tristate unused ODT pins to save power.
 405   //
 406   // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
 407   //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
 408   //      AGESA will base on this value to tristate unused Chip select to save power.
 409   //
 410   // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
 411   //      Specifies the number of DIMM slots per channel.
 412   //
 413   // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
 414   //      Specifies the number of Chip selects per channel.
 415   //
 416   // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
 417   //      Specifies the number of channels per socket.
 418   //
 419   // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
 420   //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
 421   //
 422   // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
 423   //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
 424   //
 425   // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
 426   //      Byte6Seed, Byte7Seed, ByteEccSeed)
 427   //      Specifies the write leveling seed for a channel of a socket.
 428   //
 429   // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
 430   //      Byte6Seed, Byte7Seed, ByteEccSeed)
 431   //      Speicifes the HW RXEN training seed for a channel of a socket
 432   //
 433
 434   NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
 435   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 436
 437 /*
 438   TODO: is this OK for DDR3 socket FM2?
 439   MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 440   CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
 441   ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
 442   CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 443   */
 444   PSO_END
 445 };