src/mainboard/asrock/imb-a180/PlatformGnbPcie.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include "amdlib.h"
  18 #include "Ids.h"
  19 #include "heapManager.h"
  20 #include "Filecode.h"
  21
  22 #include <northbridge/amd/agesa/agesawrapper.h>
  23
  24 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
  25
  26 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  27         {
  28                 0,
  29                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
  30                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
  31                                 HotplugDisabled,
  32                                 PcieGenMaxSupported,
  33                                 PcieGenMaxSupported,
  34                                 AspmDisabled, 0x01, 0)
  35         },
  36         /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
  37         {
  38                 0,
  39                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
  40                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
  41                                 HotplugDisabled,
  42                                 PcieGenMaxSupported,
  43                                 PcieGenMaxSupported,
  44                                 AspmDisabled, 0x02, 0)
  45         },
  46         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  47         {
  48                 0,
  49                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
  50                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
  51                                 HotplugDisabled,
  52                                 PcieGenMaxSupported,
  53                                 PcieGenMaxSupported,
  54                                 AspmDisabled, 0x03, 0)
  55         },
  56         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  57         {
  58                 0,
  59                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
  60                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
  61                                 HotplugDisabled,
  62                                 PcieGenMaxSupported,
  63                                 PcieGenMaxSupported,
  64                                 AspmDisabled, 0x04, 0)
  65         },
  66         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
  67         {
  68                 DESCRIPTOR_TERMINATE_LIST,
  69                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
  70                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
  71                                 HotplugDisabled,
  72                                 PcieGenMaxSupported,
  73                                 PcieGenMaxSupported,
  74                                 AspmDisabled, 0x05, 0)
  75         }
  76 };
  77
  78 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
  79         /* DP0 to HDMI0/DP */
  80         {
  81                 0,
  82                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
  83                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
  84         },
  85         /* DP1 to FCH */
  86         {
  87                 0,
  88                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
  89                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
  90         },
  91         /* DP2 to HDMI1/DP */
  92         {
  93                 DESCRIPTOR_TERMINATE_LIST,
  94                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
  95                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
  96         },
  97 };
  98
  99 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 100         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 101         .SocketId     = 0,
 102         .PciePortList = PortList,
 103         .DdiLinkList  = DdiList
 104 };
 105
 106 /*---------------------------------------------------------------------------------------*/
 107 /**
 108  *  OemCustomizeInitEarly
 109  *
 110  *  Description:
 111  *    This is the stub function will call the host environment through the binary block
 112  *    interface (call-out port) to provide a user hook opportunity
 113  *
 114  *  Parameters:
 115  *    @param[in]      *InitEarly
 116  *
 117  *    @retval         VOID
 118  *
 119  **/
 120 /*---------------------------------------------------------------------------------------*/
 121
 122 static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 123 {
 124         AGESA_STATUS            Status;
 125         PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
 126
 127         ALLOCATE_HEAP_PARAMS AllocHeapParams;
 128
 129         /* GNB PCIe topology Porting */
 130
 131         /*  */
 132         /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
 133         /*  */
 134         AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
 135
 136         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 137         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 138         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 139         ASSERT(Status == AGESA_SUCCESS);
 140
 141         PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 142         LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
 143         InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
 144         return AGESA_SUCCESS;
 145 }
 146
 147 static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
 148 {
 149         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 150         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 151         return AGESA_SUCCESS;
 152 }
 153
 154 const struct OEM_HOOK OemCustomize = {
 155         .InitEarly = OemInitEarly,
 156         .InitMid = OemInitMid,
 157 };