| blob | 6ec0fc5ed06c9df4bd69bd6337c6ce5c30792e7d |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /*
17 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
18 )
19 {
20 #include "routing.asl"
21 }
22 */
24 /* Routing is in System Bus scope */
25 Scope(\_SB) {
26 Name(PR0, Package(){
27 /* NB devices */
28 /* Bus 0, Dev 0 - RS780 Host Controller */
29 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
30 Package(){0x0001FFFF, 0, INTC, 0 },
31 Package(){0x0001FFFF, 1, INTD, 0 },
32 /* Bus 0, Dev 2 - */
33 Package(){0x0002FFFF, 0, INTC, 0 },
34 Package(){0x0002FFFF, 1, INTD, 0 },
35 Package(){0x0002FFFF, 2, INTA, 0 },
36 Package(){0x0002FFFF, 3, INTB, 0 },
37 /* Bus 0, Dev 3 - */
38 Package(){0x0003FFFF, 0, INTD, 0 },
39 Package(){0x0003FFFF, 1, INTA, 0 },
40 Package(){0x0003FFFF, 2, INTB, 0 },
41 Package(){0x0003FFFF, 3, INTC, 0 },
42 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
43 Package(){0x0004FFFF, 0, INTA, 0 },
44 Package(){0x0004FFFF, 1, INTB, 0 },
45 Package(){0x0004FFFF, 2, INTC, 0 },
46 Package(){0x0004FFFF, 3, INTD, 0 },
47 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
48 Package(){0x0005FFFF, 0, INTB, 0 },
49 Package(){0x0005FFFF, 1, INTC, 0 },
50 Package(){0x0005FFFF, 2, INTD, 0 },
51 Package(){0x0005FFFF, 3, INTA, 0 },
52 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
53 Package(){0x0006FFFF, 0, INTC, 0 },
54 Package(){0x0006FFFF, 1, INTD, 0 },
55 Package(){0x0006FFFF, 2, INTA, 0 },
56 Package(){0x0006FFFF, 3, INTB, 0 },
57 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
58 Package(){0x0007FFFF, 0, INTD, 0 },
59 Package(){0x0007FFFF, 1, INTA, 0 },
60 Package(){0x0007FFFF, 2, INTB, 0 },
61 Package(){0x0007FFFF, 3, INTC, 0 },
63 /* SB devices */
64 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
65 Package(){0x0014FFFF, 0, INTA, 0 },
66 Package(){0x0014FFFF, 1, INTB, 0 },
67 Package(){0x0014FFFF, 2, INTC, 0 },
68 Package(){0x0014FFFF, 3, INTD, 0 },
69 /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
70 Package(){0x0012FFFF, 0, INTC, 0 },
71 Package(){0x0012FFFF, 1, INTB, 0 },
72 Package(){0x0013FFFF, 0, INTC, 0 },
73 Package(){0x0013FFFF, 1, INTB, 0 },
74 Package(){0x0016FFFF, 0, INTC, 0 },
75 Package(){0x0016FFFF, 1, INTB, 0 },
76 Package(){0x0010FFFF, 0, INTC, 0 },
77 Package(){0x0010FFFF, 1, INTB, 0 },
78 /* Bus 0, Dev 17 - SATA controller #2 */
79 Package(){0x0011FFFF, 0, INTD, 0 },
80 /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
81 Package(){0x0015FFFF, 0, INTA, 0 },
82 Package(){0x0015FFFF, 1, INTB, 0 },
83 Package(){0x0015FFFF, 2, INTC, 0 },
84 Package(){0x0015FFFF, 3, INTD, 0 },
85 })
87 Name(APR0, Package(){
88 /* NB devices in APIC mode */
89 /* Bus 0, Dev 0 - RS780 Host Controller */
90 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
91 Package(){0x0001FFFF, 0, 0, 18 },
92 Package(){0x0001FFFF, 1, 0, 19 },
93 /* Bus 0, Dev 2 */
94 Package(){0x0002FFFF, 0, 0, 18 },
95 Package(){0x0002FFFF, 1, 0, 19 },
96 Package(){0x0002FFFF, 2, 0, 16 },
97 Package(){0x0002FFFF, 3, 0, 17 },
98 /* Bus 0, Dev 3 */
99 Package(){0x0003FFFF, 0, 0, 19 },
100 Package(){0x0003FFFF, 1, 0, 16 },
101 Package(){0x0003FFFF, 2, 0, 17 },
102 Package(){0x0003FFFF, 3, 0, 18 },
103 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
104 Package(){0x0004FFFF, 0, 0, 16 },
105 Package(){0x0004FFFF, 1, 0, 17 },
106 Package(){0x0004FFFF, 2, 0, 18 },
107 Package(){0x0004FFFF, 3, 0, 19 },
108 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
109 Package(){0x0005FFFF, 0, 0, 17 },
110 Package(){0x0005FFFF, 1, 0, 18 },
111 Package(){0x0005FFFF, 2, 0, 19 },
112 Package(){0x0005FFFF, 3, 0, 16 },
113 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
114 Package(){0x0006FFFF, 0, 0, 18 },
115 Package(){0x0006FFFF, 1, 0, 19 },
116 Package(){0x0006FFFF, 2, 0, 16 },
117 Package(){0x0006FFFF, 3, 0, 17 },
118 /* Bus 0, Dev 7 - PCIe Bridge for network card */
119 Package(){0x0007FFFF, 0, 0, 19 },
120 Package(){0x0007FFFF, 1, 0, 16 },
121 Package(){0x0007FFFF, 2, 0, 17 },
122 Package(){0x0007FFFF, 3, 0, 18 },
124 /* SB devices in APIC mode */
125 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
126 Package(){0x0014FFFF, 0, 0, 16 },
127 Package(){0x0014FFFF, 1, 0, 17 },
128 Package(){0x0014FFFF, 2, 0, 18 },
129 Package(){0x0014FFFF, 3, 0, 19 },
130 /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
131 Package(){0x0012FFFF, 0, 0, 18 },
132 Package(){0x0012FFFF, 1, 0, 17 },
133 Package(){0x0013FFFF, 0, 0, 18 },
134 Package(){0x0013FFFF, 1, 0, 17 },
135 Package(){0x0016FFFF, 0, 0, 18 },
136 Package(){0x0016FFFF, 1, 0, 17 },
137 Package(){0x0010FFFF, 0, 0, 18 },
138 Package(){0x0010FFFF, 1, 0, 17 },
139 /* Bus 0, Dev 17 - SATA controller #2 */
140 Package(){0x0011FFFF, 0, 0, 19 },
141 /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
142 Package(){0x0015FFFF, 0, 0, 16 },
143 Package(){0x0015FFFF, 1, 0, 17 },
144 Package(){0x0015FFFF, 2, 0, 18 },
145 Package(){0x0015FFFF, 3, 0, 19 },
146 })
148 Name(PS2, Package(){
149 /* For Device(PBR2) PIC mode*/
150 Package(){0x0000FFFF, 0, INTC, 0 },
151 Package(){0x0000FFFF, 1, INTD, 0 },
152 Package(){0x0000FFFF, 2, INTA, 0 },
153 Package(){0x0000FFFF, 3, INTB, 0 },
154 })
156 Name(APS2, Package(){
157 /* For Device(PBR2) APIC mode*/
158 Package(){0x0000FFFF, 0, 0, 18 },
159 Package(){0x0000FFFF, 1, 0, 19 },
160 Package(){0x0000FFFF, 2, 0, 16 },
161 Package(){0x0000FFFF, 3, 0, 17 },
162 })
164 Name(PS3, Package(){
165 /* For Device(PBR3) PIC mode*/
166 Package(){0x0000FFFF, 0, INTD, 0 },
167 Package(){0x0000FFFF, 1, INTA, 0 },
168 Package(){0x0000FFFF, 2, INTB, 0 },
169 Package(){0x0000FFFF, 3, INTC, 0 },
170 })
172 Name(APS3, Package(){
173 /* For Device(PBR3) APIC mode*/
174 Package(){0x0000FFFF, 0, 0, 19 },
175 Package(){0x0000FFFF, 1, 0, 16 },
176 Package(){0x0000FFFF, 2, 0, 17 },
177 Package(){0x0000FFFF, 3, 0, 18 },
178 })
180 Name(PS4, Package(){
181 /* For Device(PBR4) PIC mode*/
182 Package(){0x0000FFFF, 0, INTA, 0 },
183 Package(){0x0000FFFF, 1, INTB, 0 },
184 Package(){0x0000FFFF, 2, INTC, 0 },
185 Package(){0x0000FFFF, 3, INTD, 0 },
186 })
188 Name(APS4, Package(){
189 /* For Device(PBR4) APIC mode*/
190 Package(){0x0000FFFF, 0, 0, 16 },
191 Package(){0x0000FFFF, 1, 0, 17 },
192 Package(){0x0000FFFF, 2, 0, 18 },
193 Package(){0x0000FFFF, 3, 0, 19 },
194 })
196 Name(PS5, Package(){
197 /* For Device(PBR5) PIC mode*/
198 Package(){0x0000FFFF, 0, INTB, 0 },
199 Package(){0x0000FFFF, 1, INTC, 0 },
200 Package(){0x0000FFFF, 2, INTD, 0 },
201 Package(){0x0000FFFF, 3, INTA, 0 },
202 })
204 Name(APS5, Package(){
205 /* For Device(PBR5) APIC mode*/
206 Package(){0x0000FFFF, 0, 0, 17 },
207 Package(){0x0000FFFF, 1, 0, 18 },
208 Package(){0x0000FFFF, 2, 0, 19 },
209 Package(){0x0000FFFF, 3, 0, 16 },
210 })
212 Name(PS6, Package(){
213 /* For Device(PBR6) PIC mode*/
214 Package(){0x0000FFFF, 0, INTC, 0 },
215 Package(){0x0000FFFF, 1, INTD, 0 },
216 Package(){0x0000FFFF, 2, INTA, 0 },
217 Package(){0x0000FFFF, 3, INTB, 0 },
218 })
220 Name(APS6, Package(){
221 /* For Device(PBR6) APIC mode*/
222 Package(){0x0000FFFF, 0, 0, 18 },
223 Package(){0x0000FFFF, 1, 0, 19 },
224 Package(){0x0000FFFF, 2, 0, 16 },
225 Package(){0x0000FFFF, 3, 0, 17 },
226 })
228 Name(PS7, Package(){
229 /* For Device(PBR7) PIC mode*/
230 Package(){0x0000FFFF, 0, INTD, 0 },
231 Package(){0x0000FFFF, 1, INTA, 0 },
232 Package(){0x0000FFFF, 2, INTB, 0 },
233 Package(){0x0000FFFF, 3, INTC, 0 },
234 })
236 Name(APS7, Package(){
237 /* For Device(PBR7) APIC mode*/
238 Package(){0x0000FFFF, 0, 0, 19 },
239 Package(){0x0000FFFF, 1, 0, 16 },
240 Package(){0x0000FFFF, 2, 0, 17 },
241 Package(){0x0000FFFF, 3, 0, 18 },
242 })
244 Name(PE0, Package(){
245 /* For Device(PE20) PIC mode*/
246 Package(){0x0000FFFF, 0, INTA, 0 },
247 Package(){0x0000FFFF, 1, INTB, 0 },
248 Package(){0x0000FFFF, 2, INTC, 0 },
249 Package(){0x0000FFFF, 3, INTD, 0 },
250 })
252 Name(APE0, Package(){
253 /* For Device(PE20) APIC mode*/
254 Package(){0x0000FFFF, 0, 0, 16 },
255 Package(){0x0000FFFF, 1, 0, 17 },
256 Package(){0x0000FFFF, 2, 0, 18 },
257 Package(){0x0000FFFF, 3, 0, 19 },
258 })
260 Name(PE1, Package(){
261 /* For Device(PE21) PIC mode*/
262 Package(){0x0000FFFF, 0, INTB, 0 },
263 Package(){0x0000FFFF, 1, INTC, 0 },
264 Package(){0x0000FFFF, 2, INTD, 0 },
265 Package(){0x0000FFFF, 3, INTA, 0 },
266 })
268 Name(APE1, Package(){
269 /* For Device(PE21) APIC mode*/
270 Package(){0x0000FFFF, 0, 0, 17 },
271 Package(){0x0000FFFF, 1, 0, 18 },
272 Package(){0x0000FFFF, 2, 0, 19 },
273 Package(){0x0000FFFF, 3, 0, 16 },
274 })
276 Name(PE2, Package(){
277 /* For Device(PE22) PIC mode*/
278 Package(){0x0000FFFF, 0, INTC, 0 },
279 Package(){0x0000FFFF, 1, INTD, 0 },
280 Package(){0x0000FFFF, 2, INTA, 0 },
281 Package(){0x0000FFFF, 3, INTB, 0 },
282 })
284 Name(APE2, Package(){
285 /* For Device(PE22) APIC mode*/
286 Package(){0x0000FFFF, 0, 0, 18 },
287 Package(){0x0000FFFF, 1, 0, 19 },
288 Package(){0x0000FFFF, 2, 0, 16 },
289 Package(){0x0000FFFF, 3, 0, 17 },
290 })
292 Name(PE3, Package(){
293 /* For Device(PE23) PIC mode*/
294 Package(){0x0000FFFF, 0, INTD, 0 },
295 Package(){0x0000FFFF, 1, INTA, 0 },
296 Package(){0x0000FFFF, 2, INTB, 0 },
297 Package(){0x0000FFFF, 3, INTC, 0 },
298 })
300 Name(APE3, Package(){
301 /* For Device(PE23) APIC mode*/
302 Package(){0x0000FFFF, 0, 0, 19 },
303 Package(){0x0000FFFF, 1, 0, 16 },
304 Package(){0x0000FFFF, 2, 0, 17 },
305 Package(){0x0000FFFF, 3, 0, 18 },
306 })
307 }