src/mainboard/amd/thatcher/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <string.h>
  18 #include <device/pci_def.h>
  19 #include <device/pci_ids.h>
  20 #include <arch/acpi.h>
  21 #include <arch/io.h>
  22 #include <arch/stages.h>
  23 #include <device/pnp_def.h>
  24 #include <arch/cpu.h>
  25 #include <cpu/x86/lapic.h>
  26 #include <console/console.h>
  27 #include <commonlib/loglevel.h>
  28 #include <cpu/amd/car.h>
  29 #include <northbridge/amd/agesa/agesawrapper.h>
  30 #include <cpu/x86/bist.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <southbridge/amd/agesa/hudson/hudson.h>
  33 #include <superio/smsc/lpc47n217/early_serial.c>
  34 #include <cpu/amd/agesa/s3_resume.h>
  35 #include "cbmem.h"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1)
  38
  39
  40 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  41 {
  42         u32 val;
  43         u8 byte;
  44         pci_devfn_t dev;
  45
  46         amd_initmmio();
  47
  48         /* Set LPC decode enables. */
  49         dev = PCI_DEV(0, 0x14, 3);
  50         pci_write_config32(dev, 0x44, 0xff03ffd5);
  51
  52         hudson_lpc_port80();
  53         byte = pci_read_config8(dev, 0x48);
  54         byte |= 3;              /* 2e, 2f */
  55         pci_write_config8(dev, 0x48, byte);
  56
  57         if (!cpu_init_detectedx && boot_cpu()) {
  58                 post_code(0x30);
  59
  60                 post_code(0x31);
  61                 lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  62                 outb(0x24, 0xcd6);
  63                 outb(0x1, 0xcd7);
  64                 outb(0xea, 0xcd6);
  65                 outb(0x1, 0xcd7);
  66                 *(u8 *)0xfed80101 = 0x98;
  67                 console_init();
  68         }
  69
  70         /* Halt if there was a built in self test failure */
  71         post_code(0x34);
  72         report_bist_failure(bist);
  73
  74         /* Load MPB */
  75         val = cpuid_eax(1);
  76         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
  77         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
  78
  79         post_code(0x37);
  80         agesawrapper_amdinitreset();
  81         post_code(0x39);
  82
  83         agesawrapper_amdinitearly();
  84         int s3resume = acpi_is_wakeup_s3();
  85         if (!s3resume) {
  86                 post_code(0x40);
  87                 agesawrapper_amdinitpost();
  88                 post_code(0x41);
  89                 agesawrapper_amdinitenv();
  90                 disable_cache_as_ram();
  91         } else {                /* S3 detect */
  92                 printk(BIOS_INFO, "S3 detected\n");
  93
  94                 post_code(0x60);
  95                 agesawrapper_amdinitresume();
  96
  97                 amd_initcpuio();
  98                 agesawrapper_amds3laterestore();
  99
 100                 post_code(0x61);
 101                 prepare_for_resume();
 102         }
 103
 104         post_code(0x50);
 105         copy_and_run();
 106
 107         post_code(0x54);  /* Should never see this post code. */
 108 }