src/mainboard/amd/thatcher/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <arch/smp/mpspec.h>
  18 #include <device/pci.h>
  19 #include <arch/io.h>
  20 #include <arch/ioapic.h>
  21 #include <string.h>
  22 #include <stdint.h>
  23 #include <cpu/amd/amdfam15.h>
  24 #include <arch/cpu.h>
  25 #include <cpu/x86/lapic.h>
  26 #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
  27
  28 u8 picr_data[] = {
  29         0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  30         0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  31         0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  32         0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  33         0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  34         0x1F,0x1F,0x1F,0x1F
  35 };
  36 u8 intr_data[0x54] = {
  37         0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  38         0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  39         0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  40         0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  41         0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  42         0x10,0x11,0x12,0x13
  43 };
  44
  45 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
  46 {
  47         mc->mpc_length += length;
  48         mc->mpc_entry_count++;
  49 }
  50
  51 static void my_smp_write_bus(struct mp_config_table *mc,
  52                              unsigned char id, const char *bustype)
  53 {
  54         struct mpc_config_bus *mpc;
  55         mpc = smp_next_mpc_entry(mc);
  56         memset(mpc, '\0', sizeof(*mpc));
  57         mpc->mpc_type = MP_BUS;
  58         mpc->mpc_busid = id;
  59         memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
  60         smp_add_mpc_entry(mc, sizeof(*mpc));
  61 }
  62
  63 static void *smp_write_config_table(void *v)
  64 {
  65         struct mp_config_table *mc;
  66         int bus_isa;
  67         u8 byte;
  68
  69         /*
  70          * By the time this function gets called, the IOAPIC registers
  71          * have been written so they can be read to get the correct
  72          * APIC ID and Version
  73          */
  74         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  75         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  76
  77         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  78
  79         mptable_init(mc, LOCAL_APIC_ADDR);
  80         memcpy(mc->mpc_oem, "AMD     ", 8);
  81
  82         smp_write_processors(mc);
  83
  84         //mptable_write_buses(mc, NULL, &bus_isa);
  85         my_smp_write_bus(mc, 0, "PCI   ");
  86         my_smp_write_bus(mc, 1, "PCI   ");
  87         bus_isa = 0x02;
  88         my_smp_write_bus(mc, bus_isa, "ISA   ");
  89
  90         /* I/O APICs:   APIC ID Version State   Address */
  91         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  92
  93         /* PIC IRQ routine */
  94         for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
  95                 outb(byte, 0xC00);
  96                 outb(picr_data[byte], 0xC01);
  97         }
  98
  99         /* APIC IRQ routine */
 100         for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
 101                 outb(byte | 0x80, 0xC00);
 102                 outb(intr_data[byte], 0xC01);
 103         }
 104
 105         /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 106 #define IO_LOCAL_INT(type, intr, apicid, pin)                           \
 107         smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 108         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
 109
 110         /* PCI interrupts are level triggered, and are
 111          * associated with a specific bus/device/function tuple.
 112          */
 113 #define PCI_INT(bus, dev, int_sign, pin)                                \
 114         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
 115
 116         /* Internal VGA */
 117         PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
 118         PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 119
 120         /* SMBUS */
 121         PCI_INT(0x0, 0x14, 0x0, 0x10);
 122
 123         /* HD Audio */
 124         PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
 125
 126         /* USB */
 127         PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
 128         PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
 129         PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
 130         PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
 131         PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
 132         PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 133         PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
 134
 135         /* sata */
 136         PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
 137         PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 138
 139         /* on board NIC & Slot PCIE.  */
 140
 141         /* PCI slots */
 142         device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 143         if (dev && dev->enabled) {
 144                 u8 bus_pci = dev->link_list->secondary;
 145                 /* PCI_SLOT 0. */
 146                 PCI_INT(bus_pci, 0x5, 0x0, 0x14);
 147                 PCI_INT(bus_pci, 0x5, 0x1, 0x15);
 148                 PCI_INT(bus_pci, 0x5, 0x2, 0x16);
 149                 PCI_INT(bus_pci, 0x5, 0x3, 0x17);
 150
 151                 /* PCI_SLOT 1. */
 152                 PCI_INT(bus_pci, 0x6, 0x0, 0x15);
 153                 PCI_INT(bus_pci, 0x6, 0x1, 0x16);
 154                 PCI_INT(bus_pci, 0x6, 0x2, 0x17);
 155                 PCI_INT(bus_pci, 0x6, 0x3, 0x14);
 156
 157                 /* PCI_SLOT 2. */
 158                 PCI_INT(bus_pci, 0x7, 0x0, 0x16);
 159                 PCI_INT(bus_pci, 0x7, 0x1, 0x17);
 160                 PCI_INT(bus_pci, 0x7, 0x2, 0x14);
 161                 PCI_INT(bus_pci, 0x7, 0x3, 0x15);
 162         }
 163
 164         /* PCIe Lan*/
 165         PCI_INT(0x0, 0x06, 0x0, 0x13);
 166
 167         /* FCH PCIe PortA */
 168         PCI_INT(0x0, 0x15, 0x0, 0x10);
 169         /* FCH PCIe PortB */
 170         PCI_INT(0x0, 0x15, 0x1, 0x11);
 171         /* FCH PCIe PortC */
 172         PCI_INT(0x0, 0x15, 0x2, 0x12);
 173         /* FCH PCIe PortD */
 174         PCI_INT(0x0, 0x15, 0x3, 0x13);
 175
 176         /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 177         IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
 178         IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
 179         /* There is no extension information... */
 180
 181         /* Compute the checksums */
 182         return mptable_finalize(mc);
 183 }
 184
 185 unsigned long write_smp_table(unsigned long addr)
 186 {
 187         void *v;
 188         v = smp_write_floating_table(addr, 0);
 189         return (unsigned long)smp_write_config_table(v);
 190 }