?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / amd / thatcher / buildOpts.c
blob94d842a836244937b62e008fa21d9f27b05ff397
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 /**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
26 */
27
28 #include <stdlib.h>
29 #include "AGESA.h"
30 #include "Filecode.h"
31 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
32
33 /* Select the cpu family. */
34 #define INSTALL_FAMILY_10_SUPPORT FALSE
35 #define INSTALL_FAMILY_12_SUPPORT FALSE
36 #define INSTALL_FAMILY_14_SUPPORT FALSE
37 #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
38
39 /* Select the cpu socket type. */
40 #define INSTALL_G34_SOCKET_SUPPORT FALSE
41 #define INSTALL_C32_SOCKET_SUPPORT FALSE
42 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
43 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
44 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
45 #define INSTALL_FS1_SOCKET_SUPPORT TRUE
46 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
47 #define INSTALL_FP2_SOCKET_SUPPORT TRUE
48 #define INSTALL_FT1_SOCKET_SUPPORT FALSE
49 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
50
51 #define INSTALL_FM2_SOCKET_SUPPORT FALSE
52
53 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
54 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
55 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
56 //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
57 //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
58 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
59 #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
60 #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
61 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
62 //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
63 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
64 //#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
65 #define BLDOPT_REMOVE_SRAT FALSE //TRUE
66 #define BLDOPT_REMOVE_SLIT FALSE //TRUE
67 #define BLDOPT_REMOVE_WHEA FALSE //TRUE
68 #define BLDOPT_REMOVE_CRAT TRUE
69 #define BLDOPT_REMOVE_DMI TRUE
70 //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
71 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
72 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
73 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
74 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
75 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
76
77 //This element selects whether P-States should be forced to be independent,
78 // as reported by the ACPI _PSD object. For single-link processors,
79 // setting TRUE for OS to support this feature.
80
81 //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
82
83 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
84 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
85 /* Build configuration values here.
86 */
87 #define BLDCFG_VRM_CURRENT_LIMIT 90000
88 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
89 #define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
90 #define BLDCFG_PLAT_NUM_IO_APICS 3
91 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
92 #define BLDCFG_MEM_INIT_PSTATE 0
93
94 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
95
96 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
97 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
98 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
99 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
100 #define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
101 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
102 #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
103 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
104 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
105 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
106 #define BLDCFG_MEMORY_POWER_DOWN TRUE
107 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
108 #define BLDCFG_ONLINE_SPARE FALSE
109 #define BLDCFG_BANK_SWIZZLE TRUE
110 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
111 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
112 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
113 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
114 #define BLDCFG_USE_BURST_MODE FALSE
115 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
116 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
117 #define BLDCFG_ECC_REDIRECTION FALSE
118 #define BLDCFG_SCRUB_DRAM_RATE 0
119 #define BLDCFG_SCRUB_L2_RATE 0
120 #define BLDCFG_SCRUB_L3_RATE 0
121 #define BLDCFG_SCRUB_IC_RATE 0
122 #define BLDCFG_SCRUB_DC_RATE 0
123 #define BLDCFG_ECC_SYMBOL_SIZE 4
124 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
125 #define BLDCFG_ECC_SYNC_FLOOD FALSE
126 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
127 #define BLDCFG_1GB_ALIGN FALSE
128 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
129 #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
130 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
131
132 #define BLDOPT_REMOVE_ALIB FALSE
133 #define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
134 #define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
135 #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
136 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
137
138 #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
139 #define BLDCFG_CFG_ABM_SUPPORT 0
140
141 //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
142
143 // Specify the default values for the VRM controlling the VDDNB plane.
144 // If not specified, the values used for the core VRM will be applied
145 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
146 //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
147 //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
148 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
149 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
150 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
151
152 #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
153
154 #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
155 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
156
157 #if CONFIG_GFXUMA
158 #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
159 #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
160 //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
161 #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
162 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
163 #endif
164
165 #define BLDCFG_IOMMU_SUPPORT FALSE
166
167 #define BLDCFG_CFG_GNB_HD_AUDIO TRUE
168 //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
169 //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
170 //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
171
172 /* Process the options...
173 * This file include MUST occur AFTER the user option selection settings
174 */
175 #define AGESA_ENTRY_INIT_RESET TRUE
176 #define AGESA_ENTRY_INIT_RECOVERY FALSE
177 #define AGESA_ENTRY_INIT_EARLY TRUE
178 #define AGESA_ENTRY_INIT_POST TRUE
179 #define AGESA_ENTRY_INIT_ENV TRUE
180 #define AGESA_ENTRY_INIT_MID TRUE
181 #define AGESA_ENTRY_INIT_LATE TRUE
182 #define AGESA_ENTRY_INIT_S3SAVE TRUE
183 #define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
184 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
185 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
186 /*
187 * Customized OEM build configurations for FCH component
188 */
189 // #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
190 // #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
191 // #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
192 // #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
193 // #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
194 // #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
195 // #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
196 // #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
197 // #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
198 // #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
199 // #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
200 // #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
201 // #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
202 // #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
203 // #define BLDCFG_AZALIA_SSID 0x780D1022
204 // #define BLDCFG_SMBUS_SSID 0x780B1022
205 // #define BLDCFG_IDE_SSID 0x780C1022
206 // #define BLDCFG_SATA_AHCI_SSID 0x78011022
207 // #define BLDCFG_SATA_IDE_SSID 0x78001022
208 // #define BLDCFG_SATA_RAID5_SSID 0x78031022
209 // #define BLDCFG_SATA_RAID_SSID 0x78021022
210 // #define BLDCFG_EHCI_SSID 0x78081022
211 // #define BLDCFG_OHCI_SSID 0x78071022
212 // #define BLDCFG_LPC_SSID 0x780E1022
213 // #define BLDCFG_SD_SSID 0x78061022
214 // #define BLDCFG_XHCI_SSID 0x78121022
215 // #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
216 // #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
217 // #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
218 // #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
219 // #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
220 // #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
221 // #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
222 // #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
223 // #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
224 // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
225 // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
226
227 CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
228 {
229 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
230 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
231 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
232 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
233 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
234 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
235 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
236 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
237 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
238 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
239 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
240 { CPU_LIST_TERMINAL }
241 };
242
243 #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
244
245
246 /* Include the files that instantiate the configuration definitions. */
247 #include "cpuRegisters.h"
248 #include "cpuFamRegisters.h"
249 #include "cpuFamilyTranslation.h"
250 #include "AdvancedApi.h"
251 #include "heapManager.h"
252 #include "CreateStruct.h"
253 #include "cpuFeatures.h"
254 #include "Table.h"
255 #include "CommonReturns.h"
256 #include "cpuEarlyInit.h"
257 #include "cpuLateInit.h"
258 #include "GnbInterface.h"
259
260 // This is the delivery package title, "BrazosPI"
261 // This string MUST be exactly 8 characters long
262 #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
263
264 // This is the release version number of the AGESA component
265 // This string MUST be exactly 12 characters long
266 #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
267
268 /* MEMORY_BUS_SPEED */
269 #define DDR400_FREQUENCY 200 ///< DDR 400
270 #define DDR533_FREQUENCY 266 ///< DDR 533
271 #define DDR667_FREQUENCY 333 ///< DDR 667
272 #define DDR800_FREQUENCY 400 ///< DDR 800
273 #define DDR1066_FREQUENCY 533 ///< DDR 1066
274 #define DDR1333_FREQUENCY 667 ///< DDR 1333
275 #define DDR1600_FREQUENCY 800 ///< DDR 1600
276 #define DDR1866_FREQUENCY 933 ///< DDR 1866
277 #define DDR2100_FREQUENCY 1050 ///< DDR 2100
278 #define DDR2133_FREQUENCY 1066 ///< DDR 2133
279 #define DDR2400_FREQUENCY 1200 ///< DDR 2400
280 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
281
282 /* QUANDRANK_TYPE*/
283 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
284 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
285
286 /* USER_MEMORY_TIMING_MODE */
287 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
288 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
289 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
290
291 /* POWER_DOWN_MODE */
292 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
293 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
294
295 /*
296 * Agesa optional capabilities selection.
297 * Uncomment and mark FALSE those features you wish to include in the build.
298 * Comment out or mark TRUE those features you want to REMOVE from the build.
299 */
300
301 #define DFLT_SMBUS0_BASE_ADDRESS 0xB00
302 #define DFLT_SMBUS1_BASE_ADDRESS 0xB20
303 #define DFLT_SIO_PME_BASE_ADDRESS 0xE00
304 #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
305 #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
306 #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
307 #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
308 #define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
309 #define DFLT_SPI_BASE_ADDRESS 0xFEC10000
310 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
311 #define DFLT_HPET_BASE_ADDRESS 0xFED00000
312 #define DFLT_SMI_CMD_PORT 0xB0
313 #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
314 #define DFLT_GEC_BASE_ADDRESS 0xFED61000
315 #define DFLT_AZALIA_SSID 0x780D1022
316 #define DFLT_SMBUS_SSID 0x780B1022
317 #define DFLT_IDE_SSID 0x780C1022
318 #define DFLT_SATA_AHCI_SSID 0x78011022
319 #define DFLT_SATA_IDE_SSID 0x78001022
320 #define DFLT_SATA_RAID5_SSID 0x78031022
321 #define DFLT_SATA_RAID_SSID 0x78021022
322 #define DFLT_EHCI_SSID 0x78081022
323 #define DFLT_OHCI_SSID 0x78071022
324 #define DFLT_LPC_SSID 0x780E1022
325 #define DFLT_SD_SSID 0x78061022
326 #define DFLT_XHCI_SSID 0x78121022
327 #define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
328 #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
329 #define DFLT_FCH_GPP_LINK_CONFIG PortA4
330 #define DFLT_FCH_GPP_PORT0_PRESENT FALSE
331 #define DFLT_FCH_GPP_PORT1_PRESENT FALSE
332 #define DFLT_FCH_GPP_PORT2_PRESENT FALSE
333 #define DFLT_FCH_GPP_PORT3_PRESENT FALSE
334 #define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
335 #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
336 #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
337 #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
338 //#define BLDCFG_IR_PIN_CONTROL 0x33
339 #define FCH_NO_XHCI_SUPPORT TRUE
340 GPIO_CONTROL thatcher_gpio[] = {
341 {183, Function1, PullUpB},
342 {-1}
343 };
344 #define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0])
345
346 // The following definitions specify the default values for various parameters in which there are
347 // no clearly defined defaults to be used in the common file. The values below are based on product
348 // and BKDG content, please consult the AGESA Memory team for consultation.
349 #define DFLT_SCRUB_DRAM_RATE (0)
350 #define DFLT_SCRUB_L2_RATE (0)
351 #define DFLT_SCRUB_L3_RATE (0)
352 #define DFLT_SCRUB_IC_RATE (0)
353 #define DFLT_SCRUB_DC_RATE (0)
354 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
355 #define DFLT_VRM_SLEW_RATE (5000)
356
357 #include "PlatformInstall.h"
358
359 /*----------------------------------------------------------------------------------------
360 * CUSTOMER OVERIDES MEMORY TABLE
361 *----------------------------------------------------------------------------------------
362 */
363
364 /*
365 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
366 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
367 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
368 * use its default conservative settings.
369 */
370 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
371 //
372 // The following macros are supported (use comma to separate macros):
373 //
374 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
375 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
376 // AGESA will base on this value to disable unused MemClk to save power.
377 // Example:
378 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
379 // Bit AM3/S1g3 pin name
380 // 0 M[B,A]_CLK_H/L[0]
381 // 1 M[B,A]_CLK_H/L[1]
382 // 2 M[B,A]_CLK_H/L[2]
383 // 3 M[B,A]_CLK_H/L[3]
384 // 4 M[B,A]_CLK_H/L[4]
385 // 5 M[B,A]_CLK_H/L[5]
386 // 6 M[B,A]_CLK_H/L[6]
387 // 7 M[B,A]_CLK_H/L[7]
388 // And platform has the following routing:
389 // CS0 M[B,A]_CLK_H/L[4]
390 // CS1 M[B,A]_CLK_H/L[2]
391 // CS2 M[B,A]_CLK_H/L[3]
392 // CS3 M[B,A]_CLK_H/L[5]
393 // Then platform can specify the following macro:
394 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
395 //
396 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
397 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
398 // AGESA will base on this value to tristate unused CKE to save power.
399 //
400 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
401 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
402 // AGESA will base on this value to tristate unused ODT pins to save power.
403 //
404 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
405 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
406 // AGESA will base on this value to tristate unused Chip select to save power.
407 //
408 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
409 // Specifies the number of DIMM slots per channel.
410 //
411 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
412 // Specifies the number of Chip selects per channel.
413 //
414 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
415 // Specifies the number of channels per socket.
416 //
417 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
418 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
419 //
420 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
421 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
422 //
423 // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
424 // Byte6Seed, Byte7Seed, ByteEccSeed)
425 // Specifies the write leveling seed for a channel of a socket.
426 //
427 // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
428 // Byte6Seed, Byte7Seed, ByteEccSeed)
429 // Speicifes the HW RXEN training seed for a channel of a socket
430 //
431 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
432 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
433 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
434 CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
435 ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
436 CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
437
438 PSO_END
439 };
440
441 /*
442 * These tables are optional and may be used to adjust memory timing settings
443 */
444 #include "mm.h"
445 #include "mn.h"
ast, secure and flexible OpenSource firmware