2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 /* Routing is in System Bus scope */
20 /* Bus 0, Dev 0 - F15 Host Controller */
21 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
22 Package(){0x0001FFFF, 0, INTB, 0 },
23 Package(){0x0001FFFF, 1, INTC, 0 },
25 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
26 Package(){0x0002FFFF, 0, INTC, 0 },
27 Package(){0x0002FFFF, 1, INTD, 0 },
28 Package(){0x0002FFFF, 2, INTA, 0 },
29 Package(){0x0002FFFF, 3, INTB, 0 },
31 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
32 Package(){0x0003FFFF, 0, INTD, 0 },
33 Package(){0x0003FFFF, 1, INTA, 0 },
34 Package(){0x0003FFFF, 2, INTB, 0 },
35 Package(){0x0003FFFF, 3, INTC, 0 },
37 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
38 Package(){0x0004FFFF, 0, INTA, 0 },
39 Package(){0x0004FFFF, 1, INTB, 0 },
40 Package(){0x0004FFFF, 2, INTC, 0 },
41 Package(){0x0004FFFF, 3, INTD, 0 },
43 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
44 Package(){0x0005FFFF, 0, INTB, 0 },
45 Package(){0x0005FFFF, 1, INTC, 0 },
46 Package(){0x0005FFFF, 2, INTD, 0 },
47 Package(){0x0005FFFF, 3, INTA, 0 },
49 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
50 Package(){0x0006FFFF, 0, INTC, 0 },
51 Package(){0x0006FFFF, 1, INTD, 0 },
52 Package(){0x0006FFFF, 2, INTA, 0 },
53 Package(){0x0006FFFF, 3, INTB, 0 },
55 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
56 Package(){0x0007FFFF, 0, INTD, 0 },
57 Package(){0x0007FFFF, 1, INTA, 0 },
58 Package(){0x0007FFFF, 2, INTB, 0 },
59 Package(){0x0007FFFF, 3, INTC, 0 },
61 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
63 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
64 Package(){0x0014FFFF, 0, INTA, 0 },
65 Package(){0x0014FFFF, 1, INTB, 0 },
66 Package(){0x0014FFFF, 2, INTC, 0 },
67 Package(){0x0014FFFF, 3, INTD, 0 },
70 /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
72 Package(){0x0012FFFF, 0, INTC, 0 },
73 Package(){0x0012FFFF, 1, INTB, 0 },
75 Package(){0x0013FFFF, 0, INTC, 0 },
76 Package(){0x0013FFFF, 1, INTB, 0 },
78 Package(){0x0016FFFF, 0, INTC, 0 },
79 Package(){0x0016FFFF, 1, INTB, 0 },
81 /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
82 Package(){0x0010FFFF, 0, INTC, 0 },
83 Package(){0x0010FFFF, 1, INTB, 0 },
85 /* Bus 0, Dev 17 - SATA controller */
86 Package(){0x0011FFFF, 0, INTD, 0 },
88 /* Bus 0, Dev 21 Pcie Bridge */
89 Package(){0x0015FFFF, 0, INTA, 0 },
90 Package(){0x0015FFFF, 1, INTB, 0 },
91 Package(){0x0015FFFF, 2, INTC, 0 },
92 Package(){0x0015FFFF, 3, INTD, 0 },
96 /* NB devices in APIC mode */
97 /* Bus 0, Dev 0 - F15 Host Controller */
99 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
100 Package(){0x0001FFFF, 0, 0, 17 },
101 Package(){0x0001FFFF, 1, 0, 18 },
103 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
104 Package(){0x0002FFFF, 0, 0, 18 },
105 Package(){0x0002FFFF, 1, 0, 19 },
106 Package(){0x0002FFFF, 2, 0, 16 },
107 Package(){0x0002FFFF, 3, 0, 17 },
109 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
110 Package(){0x0003FFFF, 0, 0, 19 },
111 Package(){0x0003FFFF, 1, 0, 16 },
112 Package(){0x0003FFFF, 2, 0, 17 },
113 Package(){0x0003FFFF, 3, 0, 18 },
115 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
116 Package(){0x0004FFFF, 0, 0, 16 },
117 Package(){0x0004FFFF, 1, 0, 17 },
118 Package(){0x0004FFFF, 2, 0, 18 },
119 Package(){0x0004FFFF, 3, 0, 19 },
121 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
122 Package(){0x0005FFFF, 0, 0, 17 },
123 Package(){0x0005FFFF, 1, 0, 18 },
124 Package(){0x0005FFFF, 2, 0, 19 },
125 Package(){0x0005FFFF, 3, 0, 16 },
127 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
128 Package(){0x0006FFFF, 0, 0, 18 },
129 Package(){0x0006FFFF, 1, 0, 19 },
130 Package(){0x0006FFFF, 2, 0, 16 },
131 Package(){0x0006FFFF, 3, 0, 17 },
133 /* Bus 0, Dev 7 - PCIe Bridge for network card */
134 Package(){0x0007FFFF, 0, 0, 19 },
135 Package(){0x0007FFFF, 1, 0, 16 },
136 Package(){0x0007FFFF, 2, 0, 17 },
137 Package(){0x0007FFFF, 3, 0, 18 },
139 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
141 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
142 Package(){0x0014FFFF, 0, 0, 16 },
143 Package(){0x0014FFFF, 1, 0, 17 },
144 Package(){0x0014FFFF, 2, 0, 18 },
145 Package(){0x0014FFFF, 3, 0, 19 },
147 /* SB devices in APIC mode */
148 /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
150 Package(){0x0012FFFF, 0, 0, 18 },
151 Package(){0x0012FFFF, 1, 0, 17 },
153 Package(){0x0013FFFF, 0, 0, 18 },
154 Package(){0x0013FFFF, 1, 0, 17 },
156 Package(){0x0016FFFF, 0, 0, 18 },
157 Package(){0x0016FFFF, 1, 0, 17 },
159 /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
160 Package(){0x0010FFFF, 0, 0, 0x12},
161 Package(){0x0010FFFF, 1, 0, 0x11},
163 /* Bus 0, Dev 17 - SATA controller */
164 Package(){0x0011FFFF, 0, 0, 19 },
166 /* Bus0, Dev 21 PCIE Bridge */
167 Package(){0x0015FFFF, 0, 0, 16 },
168 Package(){0x0015FFFF, 1, 0, 17 },
169 Package(){0x0015FFFF, 2, 0, 18 },
170 Package(){0x0015FFFF, 3, 0, 19 },
174 /* The external GFX - Hooked to PCIe slot 2 */
175 Package(){0x0000FFFF, 0, INTC, 0 },
176 Package(){0x0000FFFF, 1, INTD, 0 },
177 Package(){0x0000FFFF, 2, INTA, 0 },
178 Package(){0x0000FFFF, 3, INTB, 0 },
180 Name(APS2, Package(){
181 /* The external GFX - Hooked to PCIe slot 2 */
182 Package(){0x0000FFFF, 0, 0, 18 },
183 Package(){0x0000FFFF, 1, 0, 19 },
184 Package(){0x0000FFFF, 2, 0, 16 },
185 Package(){0x0000FFFF, 3, 0, 17 },
189 /* PCIe slot - Hooked to PCIe slot 4 */
190 Package(){0x0000FFFF, 0, INTA, 0 },
191 Package(){0x0000FFFF, 1, INTB, 0 },
192 Package(){0x0000FFFF, 2, INTC, 0 },
193 Package(){0x0000FFFF, 3, INTD, 0 },
195 Name(APS4, Package(){
196 /* PCIe slot - Hooked to PCIe slot 4 */
197 Package(){0x0000FFFF, 0, 0, 16 },
198 Package(){0x0000FFFF, 1, 0, 17 },
199 Package(){0x0000FFFF, 2, 0, 18 },
200 Package(){0x0000FFFF, 3, 0, 19 },
204 /* PCIe slot - Hooked to PCIe slot 5 */
205 Package(){0x0000FFFF, 0, INTB, 0 },
206 Package(){0x0000FFFF, 1, INTC, 0 },
207 Package(){0x0000FFFF, 2, INTD, 0 },
208 Package(){0x0000FFFF, 3, INTA, 0 },
210 Name(APS5, Package(){
211 /* PCIe slot - Hooked to PCIe slot 5 */
212 Package(){0x0000FFFF, 0, 0, 17 },
213 Package(){0x0000FFFF, 1, 0, 18 },
214 Package(){0x0000FFFF, 2, 0, 19 },
215 Package(){0x0000FFFF, 3, 0, 16 },
219 /* PCIe slot - Hooked to PCIe slot 6 */
220 Package(){0x0000FFFF, 0, INTC, 0 },
221 Package(){0x0000FFFF, 1, INTD, 0 },
222 Package(){0x0000FFFF, 2, INTA, 0 },
223 Package(){0x0000FFFF, 3, INTB, 0 },
225 Name(APS6, Package(){
226 /* PCIe slot - Hooked to PCIe slot 6 */
227 Package(){0x0000FFFF, 0, 0, 18 },
228 Package(){0x0000FFFF, 1, 0, 19 },
229 Package(){0x0000FFFF, 2, 0, 16 },
230 Package(){0x0000FFFF, 3, 0, 17 },
234 /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
235 Package(){0x0000FFFF, 0, INTD, 0 },
236 Package(){0x0000FFFF, 1, INTA, 0 },
237 Package(){0x0000FFFF, 2, INTB, 0 },
238 Package(){0x0000FFFF, 3, INTC, 0 },
240 Name(APS7, Package(){
241 /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
242 Package(){0x0000FFFF, 0, 0, 19 },
243 Package(){0x0000FFFF, 1, 0, 16 },
244 Package(){0x0000FFFF, 2, 0, 17 },
245 Package(){0x0000FFFF, 3, 0, 18 },
249 /* PCIe slot - Hooked to PCIe Bridge 0*/
250 Package(){0x0000FFFF, 0, INTA, 0 },
251 Package(){0x0000FFFF, 1, INTB, 0 },
252 Package(){0x0000FFFF, 2, INTC, 0 },
253 Package(){0x0000FFFF, 3, INTD, 0 },
255 Name(APE0, Package(){
256 /* PCIe slot - Hooked to PCIe Bridge 0*/
257 Package(){0x0000FFFF, 0, 0, 16 },
258 Package(){0x0000FFFF, 1, 0, 17 },
259 Package(){0x0000FFFF, 2, 0, 18 },
260 Package(){0x0000FFFF, 3, 0, 19 },
264 /* PCIe slot - Hooked to PCIe Bridge 1*/
265 Package(){0x0000FFFF, 0, INTB, 0 },
266 Package(){0x0000FFFF, 1, INTC, 0 },
267 Package(){0x0000FFFF, 2, INTD, 0 },
268 Package(){0x0000FFFF, 3, INTA, 0 },
270 Name(APE1, Package(){
271 /* PCIe slot - Hooked to PCIe Bridge 1*/
272 Package(){0x0000FFFF, 0, 0, 17 },
273 Package(){0x0000FFFF, 1, 0, 18 },
274 Package(){0x0000FFFF, 2, 0, 19 },
275 Package(){0x0000FFFF, 3, 0, 16 },
279 /* PCIe slot - Hooked to PCIe Bridge 2*/
280 Package(){0x0000FFFF, 0, INTC, 0 },
281 Package(){0x0000FFFF, 1, INTD, 0 },
282 Package(){0x0000FFFF, 2, INTA, 0 },
283 Package(){0x0000FFFF, 3, INTB, 0 },
285 Name(APE2, Package(){
286 /* PCIe slot - Hooked to PCIe Bridge 2*/
287 Package(){0x0000FFFF, 0, 0, 18 },
288 Package(){0x0000FFFF, 1, 0, 19 },
289 Package(){0x0000FFFF, 2, 0, 16 },
290 Package(){0x0000FFFF, 3, 0, 17 },
294 /* PCIe slot - Hooked to PCIe Bridge 3 */
295 Package(){0x0000FFFF, 0, INTD, 0 },
296 Package(){0x0000FFFF, 1, INTA, 0 },
297 Package(){0x0000FFFF, 2, INTB, 0 },
298 Package(){0x0000FFFF, 3, INTC, 0 },
300 Name(APE3, Package(){
301 /* PCIe slot - Hooked to PCIe Bridge 3*/
302 Package(){0x0000FFFF, 0, 0, 19 },
303 Package(){0x0000FFFF, 1, 0, 16 },
304 Package(){0x0000FFFF, 2, 0, 17 },
305 Package(){0x0000FFFF, 3, 0, 18 },
308 /* SB PCI Bridge J21, J22 */
309 Name(PCIB, Package(){
310 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
311 Package(){0x0005FFFF, 0, 0, 0x14 },
312 Package(){0x0005FFFF, 1, 0, 0x15 },
313 Package(){0x0005FFFF, 2, 0, 0x16 },
314 Package(){0x0005FFFF, 3, 0, 0x17 },
316 Package(){0x0006FFFF, 0, 0, 0x15 },
317 Package(){0x0006FFFF, 1, 0, 0x16 },
318 Package(){0x0006FFFF, 2, 0, 0x17 },
319 Package(){0x0006FFFF, 3, 0, 0x14 },