src/mainboard/amd/thatcher/PlatformGnbPcie.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include "amdlib.h"
  18 #include "Ids.h"
  19 #include "heapManager.h"
  20 #include "Filecode.h"
  21
  22 #include <northbridge/amd/agesa/agesawrapper.h>
  23
  24 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
  25
  26 /*
  27  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
  28  *
  29  * Lane Id
  30  * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
  31  * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
  32  * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
  33  * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
  34  * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
  35  * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
  36  * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
  37  * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
  38  * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
  39  * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
  40  * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
  41  * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
  42  * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
  43  * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
  44  * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
  45  * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
  46  * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
  47  * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
  48  * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
  49  * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
  50  * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
  51  * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
  52  * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
  53  * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
  54  * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
  55  * 25 DP0_TX[P,N]1
  56  * 26 DP0_TX[P,N]2
  57  * 27 DP0_TX[P,N]3
  58  * 28 DP1_TX[P,N]0
  59  * 29 DP1_TX[P,N]1
  60  * 30 DP1_TX[P,N]2
  61  * 31 DP1_TX[P,N]3
  62  * 32 DP2_TX[P,N]0
  63  * 33 DP2_TX[P,N]1
  64  * 34 DP2_TX[P,N]2
  65  * 35 DP2_TX[P,N]3
  66  * 36 DP2_TX[P,N]4
  67  * 37 DP2_TX[P,N]5
  68  * 38 DP2_TX[P,N]6
  69  */
  70
  71 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  72         /* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
  73         {
  74                 0,
  75                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8),
  76                 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
  77         },
  78         /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
  79         {
  80                 0,
  81                 PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
  82                 PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
  83         },
  84
  85         /* PCIe port, Lanes 4, PCI Device Number 4, LAN */
  86         {
  87                 0,
  88                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
  89                 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
  90         },
  91
  92         /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
  93         {
  94                 0,
  95                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
  96                 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
  97         },
  98
  99         /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
 100         {
 101                 0,
 102                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
 103                 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 104         },
 105
 106         /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
 107         {
 108                 0,
 109                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
 110                 PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
 111         },
 112
 113         /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
 114         {
 115                 DESCRIPTOR_TERMINATE_LIST,
 116                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
 117                 PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
 118         },
 119 };
 120
 121 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
 122         // DP0 to HDMI0/DP0
 123         {
 124                 0,
 125                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
 126                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
 127         },
 128         // DP1 to HDMI1/DP1
 129         {
 130                 0,
 131                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
 132                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
 133         },
 134         // DP2 to MINI-DDI Card
 135         {
 136                 DESCRIPTOR_TERMINATE_LIST,
 137                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
 138                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
 139         },
 140 };
 141
 142 static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
 143         DESCRIPTOR_TERMINATE_LIST,
 144         0,
 145         &PortList[0],
 146         &DdiList[0]
 147 };
 148
 149 /*---------------------------------------------------------------------------------------*/
 150 /**
 151  *  OemCustomizeInitEarly
 152  *
 153  *  Description:
 154  *    This stub function will call the host environment through the binary block
 155  *    interface (call-out port) to provide a user hook opportunity
 156  *
 157  *  Parameters:
 158  *    @param[in]      *InitEarly
 159  *
 160  *    @retval         VOID
 161  *
 162  **/
 163 /*---------------------------------------------------------------------------------------*/
 164
 165 static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 166 {
 167         AGESA_STATUS         Status;
 168         VOID                 *TrinityPcieComplexListPtr;
 169         VOID                 *TrinityPciePortPtr;
 170         VOID                 *TrinityPcieDdiPtr;
 171
 172         ALLOCATE_HEAP_PARAMS AllocHeapParams;
 173
 174         // GNB PCIe topology Porting
 175
 176         //
 177         // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 178         //
 179         AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
 180
 181         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 182         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 183         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 184         ASSERT(Status == AGESA_SUCCESS);
 185
 186         TrinityPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 187
 188         AllocHeapParams.BufferPtr += sizeof(Trinity);
 189         TrinityPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 190
 191         AllocHeapParams.BufferPtr += sizeof(PortList);
 192         TrinityPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 193
 194         LibAmdMemFill (TrinityPcieComplexListPtr,
 195                        0,
 196                        sizeof(Trinity),
 197                        &InitEarly->StdHeader);
 198
 199         LibAmdMemFill (TrinityPciePortPtr,
 200                        0,
 201                        sizeof(PortList),
 202                        &InitEarly->StdHeader);
 203
 204         LibAmdMemFill (TrinityPcieDdiPtr,
 205                        0,
 206                        sizeof(DdiList),
 207                        &InitEarly->StdHeader);
 208
 209         LibAmdMemCopy  (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
 210         LibAmdMemCopy  (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
 211         LibAmdMemCopy  (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
 212
 213         ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
 214         ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
 215
 216         InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
 217         return AGESA_SUCCESS;
 218 }
 219
 220 static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
 221 {
 222         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 223         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 224         return AGESA_SUCCESS;
 225 }
 226
 227 const struct OEM_HOOK OemCustomize = {
 228         .InitEarly = OemInitEarly,
 229         .InitMid = OemInitMid,
 230 };