src/mainboard/amd/south_station/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <arch/io.h>
  20 #include <cpu/x86/msr.h>
  21 #include <southbridge/amd/sb800/sb800.h>
  22 #include <cpu/amd/mtrr.h>
  23 #include <device/pci_def.h>
  24 #include <delay.h>
  25 #include "SBPLATFORM.h"         /* Platfrom Specific Definitions */
  26
  27
  28 void set_pcie_reset(void);
  29 void set_pcie_dereset(void);
  30
  31 /**
  32  * TODO
  33  * SB CIMx callback
  34  */
  35 void set_pcie_reset(void)
  36 {
  37 }
  38
  39 /**
  40  * TODO
  41  * mainboard specific SB CIMx callback
  42  */
  43 void set_pcie_dereset(void)
  44 {
  45 }
  46
  47 /**
  48  * Southstation using SB GPIO 17/18 to control the Red/Green LED
  49  * These two LEDs can be used to show the OS booting status.
  50  */
  51 static void southstation_led_init(void)
  52 {
  53 #define GPIO_FUNCTION   2  //GPIO function
  54 #define SB_GPIO_REG17   17 //Red  Light
  55 #define SB_GPIO_REG18   18 //Green Light
  56
  57         /* multi-function pins switch to GPIO0-35 */
  58         RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
  59
  60         /* select IOMux to function2, corresponds to GPIO */
  61         RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
  62         RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
  63
  64         /* Lighting test */
  65         RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
  66         RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
  67         mdelay(100);
  68         RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
  69         RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
  70 }
  71
  72
  73 /**********************************************
  74  * Enable the dedicated functions of the board.
  75  **********************************************/
  76 static void mainboard_enable(device_t dev)
  77 {
  78         printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
  79         southstation_led_init();
  80
  81         /*
  82          * Initialize ASF registers to an arbitrary address because someone
  83          * long ago set things up this way inside the SPD read code.  The
  84          * SPD read code has been made generic and moved out of the board
  85          * directory, so the ASF init is being done here.
  86          */
  87         pm_iowrite(0x29, 0x80);
  88         pm_iowrite(0x28, 0x61);
  89 }
  90
  91 struct chip_operations mainboard_ops = {
  92         .enable_dev = mainboard_enable,
  93 };