2 * This file is part of the coreboot project.
4 * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 /* No IDE functionality */
23 Name(_ADR, 0x00140001)
30 /* Some timing tables */
31 Name(UDTT, Package(){ /* Udma timing table */
32 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
35 Name(MDTT, Package(){ /* MWDma timing table */
36 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
39 Name(POTT, Package(){ /* Pio timing table */
40 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
43 /* Some timing register value tables */
44 Name(MDRT, Package(){ /* MWDma timing register table */
45 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
49 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
52 OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
53 Field(ICRG, AnyAcc, NoLock, Preserve)
55 PPTS, 8, /* Primary PIO Slave Timing */
56 PPTM, 8, /* Primary PIO Master Timing */
57 OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
58 PMTM, 8, /* Primary MWDMA Master Timing */
59 OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
60 OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
61 PPSM, 4, /* Primary PIO slave Mode */
62 OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
63 OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
64 PDSM, 4, /* Primary UltraDMA Mode */
67 Method(GTTM, 1) /* get total time*/
69 Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
71 Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
73 Return(Multiply(30, Add(Local0, Local1)))
81 NAME(OTBF, Buffer(20) { /* out buffer */
82 0xFF, 0xFF, 0xFF, 0xFF,
83 0xFF, 0xFF, 0xFF, 0xFF,
84 0xFF, 0xFF, 0xFF, 0xFF,
85 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
88 CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
89 CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
90 CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
91 CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
92 CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
94 /* Just return if the channel is disabled */
95 If(And(PPCR, 0x01)) { /* primary PIO control */
99 /* Always tell them independent timing available and IOChannelReady used on both drives */
102 /* save total time of primary PIO master timing to PIO spd0 */
103 Store(GTTM(PPTM), PSD0)
104 /* save total time of primary PIO slave Timing to PIO spd1 */
105 Store(GTTM(PPTS), PSD1)
107 If(And(PDCR, 0x01)) { /* It's under UDMA mode */
109 Store(DerefOf(Index(UDTT, PDMM)), DSD0)
112 Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
115 If(And(PDCR, 0x02)) { /* It's under UDMA mode */
117 Store(DerefOf(Index(UDTT, PDSM)), DSD1)
120 Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
123 Return(OTBF) /* out buffer */
124 } /* End Method(_GTM) */
126 Method(_STM, 3, NotSerialized)
128 NAME(INBF, Buffer(20) { /* in buffer */
129 0xFF, 0xFF, 0xFF, 0xFF,
130 0xFF, 0xFF, 0xFF, 0xFF,
131 0xFF, 0xFF, 0xFF, 0xFF,
132 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
135 CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
136 CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
137 CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
138 CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
139 CreateDwordField(INBF, 16, BFFG) /*buffer flag */
141 Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
142 Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
143 Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
144 Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
146 Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
147 Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
149 If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
150 Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
151 Divide(Local0, 7, PDMM,)
155 If(LNotEqual(DSD0, 0xFFFFFFFF)) {
156 Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
157 Store(DerefOf(Index(MDRT, Local0)), PMTM)
161 If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
162 Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
163 Divide(Local0, 7, PDSM,)
167 If(LNotEqual(DSD1, 0xFFFFFFFF)) {
168 Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
169 Store(DerefOf(Index(MDRT, Local0)), PMTS)
173 } /*End Method(_STM) */
178 Name(CMBF, Buffer(21) {
179 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
180 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
183 CreateByteField(CMBF, 1, POMD)
184 CreateByteField(CMBF, 8, DMMD)
185 CreateByteField(CMBF, 5, CMDA)
186 CreateByteField(CMBF, 12, CMDB)
187 CreateByteField(CMBF, 19, CMDC)
195 If(And(PDCR, 0x01)) {
200 (MDTT, MLE, GTTM(PMTM),
202 If(LLess(Local0, 3)) {
203 Or(0x20, Local0, DMMD)
208 } /* End Device(MST) */
214 Name(CMBF, Buffer(21) {
215 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
216 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
217 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
219 CreateByteField(CMBF, 1, POMD)
220 CreateByteField(CMBF, 8, DMMD)
221 CreateByteField(CMBF, 5, CMDA)
222 CreateByteField(CMBF, 12, CMDB)
223 CreateByteField(CMBF, 19, CMDC)
231 If(And(PDCR, 0x02)) {
236 (MDTT, MLE, GTTM(PMTS),
238 If(LLess(Local0, 3)) {
239 Or(0x20, Local0, DMMD)
244 } /* End Device(SLAV) */