2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 //#define SYSTEM_TYPE 0 /* SERVER */
17 #define SYSTEM_TYPE 1 /* DESKTOP */
18 //#define SYSTEM_TYPE 2 /* MOBILE */
20 //used by incoherent_ht
21 #define FAM10_SCAN_PCI_BUS 0
22 #define FAM10_ALLOCATE_IO_RANGE 0
26 #include <device/pci_def.h>
27 #include <device/pci_ids.h>
29 #include <device/pnp_def.h>
30 #include <cpu/x86/lapic.h>
31 #include <console/console.h>
32 #include <timestamp.h>
33 #include <cpu/amd/model_10xxx_rev.h>
34 #include <northbridge/amd/amdfam10/raminit.h>
35 #include <northbridge/amd/amdfam10/amdfam10.h>
37 #include <cpu/x86/lapic.h>
38 #include "northbridge/amd/amdfam10/reset_test.c"
39 #include <commonlib/loglevel.h>
40 #include <cpu/x86/bist.h>
41 #include <superio/ite/common/ite.h>
42 #include <superio/ite/it8718f/it8718f.h>
43 #include <cpu/amd/mtrr.h>
44 #include "northbridge/amd/amdfam10/setup_resource_map.c"
45 #include "southbridge/amd/rs780/early_setup.c"
46 #include <southbridge/amd/sb700/sb700.h>
47 #include <southbridge/amd/sb700/smbus.h>
48 #include "northbridge/amd/amdfam10/debug.c"
51 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
53 static void activate_spd_rom(const struct mem_controller
*ctrl
) { }
55 static int spd_read_byte(u32 device
, u32 address
)
57 return do_smbus_read_byte(SMBUS_IO_BASE
, device
, address
);
60 #include <northbridge/amd/amdfam10/amdfam10.h>
61 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
62 #include "northbridge/amd/amdfam10/pci.c"
63 #include "resourcemap.c"
64 #include "cpu/amd/quadcore/quadcore.c"
65 #include <cpu/amd/microcode.h>
67 #include "cpu/amd/model_10xxx/init_cpus.c"
68 #include "northbridge/amd/amdfam10/early_ht.c"
70 void cache_as_ram_main(unsigned long bist
, unsigned long cpu_init_detectedx
)
72 struct sys_info
*sysinfo
= &sysinfo_car
;
73 static const u8 spd_addr
[] = {RC00
, DIMM0
, DIMM2
, 0, 0, DIMM1
, DIMM3
, 0, 0, };
74 u32 bsp_apicid
= 0, val
;
77 timestamp_init(timestamp_get());
78 timestamp_add_now(TS_START_ROMSTAGE
);
80 if (!cpu_init_detectedx
&& boot_cpu()) {
81 /* Nothing special needs to be done to find bus 0 */
82 /* Allow the HT devices to be found */
83 /* mov bsp to bus 0xff when > 8 nodes */
84 set_bsp_node_CHtExtNodeCfgEn();
86 sb7xx_51xx_pci_port80();
92 bsp_apicid
= init_cpus(cpu_init_detectedx
, sysinfo
); /* mmconf is inited in init_cpus */
93 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
99 sb7xx_51xx_lpc_init();
101 ite_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
105 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
107 /* Halt if there was a built in self test failure */
108 report_bist_failure(bist
);
112 printk(BIOS_DEBUG
, "BSP Family_Model: %08x\n", val
);
113 printk(BIOS_DEBUG
, "*sysinfo range: [%p,%p]\n",sysinfo
,sysinfo
+1);
114 printk(BIOS_DEBUG
, "bsp_apicid = %02x\n", bsp_apicid
);
115 printk(BIOS_DEBUG
, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx
);
117 /* Setup sysinfo defaults */
118 set_sysinfo_in_ram(0);
120 update_microcode(val
);
127 amd_ht_init(sysinfo
);
130 /* Setup nodes PCI space and start core 0 AP init. */
131 finalize_node_setup(sysinfo
);
133 /* Setup any mainboard PCI settings etc. */
134 setup_mb_resource_map();
137 /* wait for all the APs core0 started by finalize_node_setup. */
138 /* FIXME: A bunch of cores are going to start output to serial at once.
139 It would be nice to fixup prink spinlocks for ROM XIP mode.
140 I think it could be done by putting the spinlock flag in the cache
141 of the BSP located right after sysinfo.
143 wait_all_core0_started();
145 #if CONFIG_LOGICAL_CPUS
146 /* Core0 on each node is configured. Now setup any additional cores. */
147 printk(BIOS_DEBUG
, "start_other_cores()\n");
150 wait_all_other_cores_started(bsp_apicid
);
155 /* run _early_setup before soft-reset. */
157 sb7xx_51xx_early_setup();
159 #if CONFIG_SET_FIDVID
160 msr
= rdmsr(0xc0010071);
161 printk(BIOS_DEBUG
, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr
.hi
, msr
.lo
);
163 /* FIXME: The sb fid change may survive the warm reset and only
164 need to be done once.*/
165 enable_fid_change_on_sb(sysinfo
->sbbusn
, sysinfo
->sbdn
);
169 if (!warm_reset_detect(0)) { // BSP is node 0
170 init_fidvid_bsp(bsp_apicid
, sysinfo
->nodes
);
172 init_fidvid_stage2(bsp_apicid
, 0); // BSP is node 0
177 /* show final fid and vid */
178 msr
=rdmsr(0xc0010071);
179 printk(BIOS_DEBUG
, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr
.hi
, msr
.lo
);
184 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
185 if (!warm_reset_detect(0)) {
186 printk(BIOS_INFO
, "...WARM RESET...\n\n\n");
188 die("After soft_reset_x - shouldn't see this message!!!\n");
193 /* It's the time to set ctrl in sysinfo now; */
194 printk(BIOS_DEBUG
, "fill_mem_ctrl()\n");
195 fill_mem_ctrl(sysinfo
->nodes
, sysinfo
->ctrl
, spd_addr
);
199 // die("Die Before MCT init.");
201 timestamp_add_now(TS_BEFORE_INITRAM
);
202 printk(BIOS_DEBUG
, "raminit_amdmct()\n");
203 raminit_amdmct(sysinfo
);
204 timestamp_add_now(TS_AFTER_INITRAM
);
206 cbmem_initialize_empty();
209 amdmct_cbmem_store_info(sysinfo
);
212 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
213 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
214 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
215 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
218 // die("After MCT init before CAR disabled.");
220 rs780_before_pci_init();
221 sb7xx_51xx_before_pci_init();
224 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
225 post_code(0x43); // Should never see this post code.
229 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
231 * This routine is called every time a non-coherent chain is processed.
232 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
233 * swap list. The first part of the list controls the BUID assignment and the
234 * second part of the list provides the device to device linking. Device orientation
235 * can be detected automatically, or explicitly. See documentation for more details.
237 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
238 * based on each device's unit count.
241 * @param[in] node = The node on which this chain is located
242 * @param[in] link = The link on the host for this chain
243 * @param[out] List = supply a pointer to a list
245 BOOL
AMD_CB_ManualBUIDSwapList (u8 node
, u8 link
, const u8
**List
)
247 static const u8 swaplist
[] = {0, 1, 0xFF, 0, 0xFF};
248 /* If the BUID was adjusted in early_ht we need to do the manual override */
249 if ((node
== 0) && (link
== 0)) { /* BSP SB link */