| blob | 56f63059d82840d5a12d9766f0dbfea795d0b5bd |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 DefinitionBlock (
18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
21 "AMD ", /* OEMID */
22 "COREBOOT", /* TABLE ID */
23 0x00010001 /* OEM Revision */
24 )
25 { /* Start of ASL file */
26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28 /* Data to be patched by the BIOS during POST */
29 /* FIXME the patching is not done yet! */
30 /* Memory related values */
31 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
32 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
33 Name(PBLN, 0x0) /* Length of BIOS area */
35 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
36 Name(HPBA, 0xFED00000) /* Base address of HPET table */
38 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
40 /* USB overcurrent mapping pins. */
41 Name(UOM0, 0)
42 Name(UOM1, 2)
43 Name(UOM2, 0)
44 Name(UOM3, 7)
45 Name(UOM4, 2)
46 Name(UOM5, 2)
47 Name(UOM6, 6)
48 Name(UOM7, 2)
49 Name(UOM8, 6)
50 Name(UOM9, 6)
52 /* Some global data */
53 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
54 Name(OSV, Ones) /* Assume nothing */
55 Name(PMOD, One) /* Assume APIC */
57 /*
58 * Processor Object
59 *
60 */
61 Scope (\_PR) { /* define processor scope */
62 Processor(
63 CPU0, /* name space name */
64 0, /* Unique number for this processor */
65 0x808, /* PBLK system I/O address !hardcoded! */
66 0x06 /* PBLKLEN for boot processor */
67 ) {
68 #include "acpi/cpstate.asl"
69 }
71 Processor(
72 CPU1, /* name space name */
73 1, /* Unique number for this processor */
74 0x0000, /* PBLK system I/O address !hardcoded! */
75 0x00 /* PBLKLEN for boot processor */
76 ) {
77 #include "acpi/cpstate.asl"
78 }
80 Processor(
81 CPU2, /* name space name */
82 2, /* Unique number for this processor */
83 0x0000, /* PBLK system I/O address !hardcoded! */
84 0x00 /* PBLKLEN for boot processor */
85 ) {
86 #include "acpi/cpstate.asl"
87 }
89 Processor(
90 CPU3, /* name space name */
91 3, /* Unique number for this processor */
92 0x0000, /* PBLK system I/O address !hardcoded! */
93 0x00 /* PBLKLEN for boot processor */
94 ) {
95 #include "acpi/cpstate.asl"
96 }
97 } /* End _PR scope */
99 /* PIC IRQ mapping registers, C00h-C01h */
100 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
101 Field(PRQM, ByteAcc, NoLock, Preserve) {
102 PRQI, 0x00000008,
103 PRQD, 0x00000008, /* Offset: 1h */
104 }
105 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
106 PINA, 0x00000008, /* Index 0 */
107 PINB, 0x00000008, /* Index 1 */
108 PINC, 0x00000008, /* Index 2 */
109 PIND, 0x00000008, /* Index 3 */
110 AINT, 0x00000008, /* Index 4 */
111 SINT, 0x00000008, /* Index 5 */
112 , 0x00000008, /* Index 6 */
113 AAUD, 0x00000008, /* Index 7 */
114 AMOD, 0x00000008, /* Index 8 */
115 PINE, 0x00000008, /* Index 9 */
116 PINF, 0x00000008, /* Index A */
117 PING, 0x00000008, /* Index B */
118 PINH, 0x00000008, /* Index C */
119 }
121 /* PCI Error control register */
122 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
123 Field(PERC, ByteAcc, NoLock, Preserve) {
124 SENS, 0x00000001,
125 PENS, 0x00000001,
126 SENE, 0x00000001,
127 PENE, 0x00000001,
128 }
130 /* Client Management index/data registers */
131 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
132 Field(CMT, ByteAcc, NoLock, Preserve) {
133 CMTI, 8,
134 /* Client Management Data register */
135 G64E, 1,
136 G64O, 1,
137 G32O, 2,
138 , 2,
139 GPSL, 2,
140 }
142 /* GPM Port register */
143 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
144 Field(GPT, ByteAcc, NoLock, Preserve) {
145 GPB0,1,
146 GPB1,1,
147 GPB2,1,
148 GPB3,1,
149 GPB4,1,
150 GPB5,1,
151 GPB6,1,
152 GPB7,1,
153 }
155 /* Flash ROM program enable register */
156 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
157 Field(FRE, ByteAcc, NoLock, Preserve) {
158 , 0x00000006,
159 FLRE, 0x00000001,
160 }
162 /* PM2 index/data registers */
163 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
164 Field(PM2R, ByteAcc, NoLock, Preserve) {
165 PM2I, 0x00000008,
166 PM2D, 0x00000008,
167 }
169 /* Power Management I/O registers */
170 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
171 Field(PIOR, ByteAcc, NoLock, Preserve) {
172 PIOI, 0x00000008,
173 PIOD, 0x00000008,
174 }
175 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
176 Offset(0x00), /* MiscControl */
177 , 1,
178 T1EE, 1,
179 T2EE, 1,
180 Offset(0x01), /* MiscStatus */
181 , 1,
182 T1E, 1,
183 T2E, 1,
184 Offset(0x04), /* SmiWakeUpEventEnable3 */
185 , 7,
186 SSEN, 1,
187 Offset(0x07), /* SmiWakeUpEventStatus3 */
188 , 7,
189 CSSM, 1,
190 Offset(0x10), /* AcpiEnable */
191 , 6,
192 PWDE, 1,
193 Offset(0x1C), /* ProgramIoEnable */
194 , 3,
195 MKME, 1,
196 IO3E, 1,
197 IO2E, 1,
198 IO1E, 1,
199 IO0E, 1,
200 Offset(0x1D), /* IOMonitorStatus */
201 , 3,
202 MKMS, 1,
203 IO3S, 1,
204 IO2S, 1,
205 IO1S, 1,
206 IO0S,1,
207 Offset(0x20), /* AcpiPmEvtBlk */
208 APEB, 16,
209 Offset(0x36), /* GEvtLevelConfig */
210 , 6,
211 ELC6, 1,
212 ELC7, 1,
213 Offset(0x37), /* GPMLevelConfig0 */
214 , 3,
215 PLC0, 1,
216 PLC1, 1,
217 PLC2, 1,
218 PLC3, 1,
219 PLC8, 1,
220 Offset(0x38), /* GPMLevelConfig1 */
221 , 1,
222 PLC4, 1,
223 PLC5, 1,
224 , 1,
225 PLC6, 1,
226 PLC7, 1,
227 Offset(0x3B), /* PMEStatus1 */
228 GP0S, 1,
229 GM4S, 1,
230 GM5S, 1,
231 APS, 1,
232 GM6S, 1,
233 GM7S, 1,
234 GP2S, 1,
235 STSS, 1,
236 Offset(0x55), /* SoftPciRst */
237 SPRE, 1,
238 , 1,
239 , 1,
240 PNAT, 1,
241 PWMK, 1,
242 PWNS, 1,
244 /* Offset(0x61), */ /* Options_1 */
245 /* ,7, */
246 /* R617,1, */
248 Offset(0x65), /* UsbPMControl */
249 , 4,
250 URRE, 1,
251 Offset(0x68), /* MiscEnable68 */
252 , 3,
253 TMTE, 1,
254 , 1,
255 Offset(0x92), /* GEVENTIN */
256 , 7,
257 E7IS, 1,
258 Offset(0x96), /* GPM98IN */
259 G8IS, 1,
260 G9IS, 1,
261 Offset(0x9A), /* EnhanceControl */
262 ,7,
263 HPDE, 1,
264 Offset(0xA8), /* PIO7654Enable */
265 IO4E, 1,
266 IO5E, 1,
267 IO6E, 1,
268 IO7E, 1,
269 Offset(0xA9), /* PIO7654Status */
270 IO4S, 1,
271 IO5S, 1,
272 IO6S, 1,
273 IO7S, 1,
274 }
276 /* PM1 Event Block
277 * First word is PM1_Status, Second word is PM1_Enable
278 */
279 OperationRegion(P1EB, SystemIO, APEB, 0x04)
280 Field(P1EB, ByteAcc, NoLock, Preserve) {
281 TMST, 1,
282 , 3,
283 BMST, 1,
284 GBST, 1,
285 Offset(0x01),
286 PBST, 1,
287 , 1,
288 RTST, 1,
289 , 3,
290 PWST, 1,
291 SPWS, 1,
292 Offset(0x02),
293 TMEN, 1,
294 , 4,
295 GBEN, 1,
296 Offset(0x03),
297 PBEN, 1,
298 , 1,
299 RTEN, 1,
300 , 3,
301 PWDA, 1,
302 }
304 Scope(\_SB) {
305 /* PCIe Configuration Space for 16 busses */
306 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
307 Field(PCFG, ByteAcc, NoLock, Preserve) {
308 /* Byte offsets are computed using the following technique:
309 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
310 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
311 */
312 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
313 STB5, 32,
314 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
315 PT0D, 1,
316 PT1D, 1,
317 PT2D, 1,
318 PT3D, 1,
319 PT4D, 1,
320 PT5D, 1,
321 PT6D, 1,
322 PT7D, 1,
323 PT8D, 1,
324 PT9D, 1,
325 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
326 SBIE, 1,
327 SBME, 1,
328 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
329 SBRI, 8,
330 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
331 SBB1, 32,
332 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
333 ,14,
334 P92E, 1, /* Port92 decode enable */
335 }
337 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
338 Field(SB5, AnyAcc, NoLock, Preserve){
339 /* Port 0 */
340 Offset(0x120), /* Port 0 Task file status */
341 P0ER, 1,
342 , 2,
343 P0DQ, 1,
344 , 3,
345 P0BY, 1,
346 Offset(0x128), /* Port 0 Serial ATA status */
347 P0DD, 4,
348 , 4,
349 P0IS, 4,
350 Offset(0x12C), /* Port 0 Serial ATA control */
351 P0DI, 4,
352 Offset(0x130), /* Port 0 Serial ATA error */
353 , 16,
354 P0PR, 1,
356 /* Port 1 */
357 offset(0x1A0), /* Port 1 Task file status */
358 P1ER, 1,
359 , 2,
360 P1DQ, 1,
361 , 3,
362 P1BY, 1,
363 Offset(0x1A8), /* Port 1 Serial ATA status */
364 P1DD, 4,
365 , 4,
366 P1IS, 4,
367 Offset(0x1AC), /* Port 1 Serial ATA control */
368 P1DI, 4,
369 Offset(0x1B0), /* Port 1 Serial ATA error */
370 , 16,
371 P1PR, 1,
373 /* Port 2 */
374 Offset(0x220), /* Port 2 Task file status */
375 P2ER, 1,
376 , 2,
377 P2DQ, 1,
378 , 3,
379 P2BY, 1,
380 Offset(0x228), /* Port 2 Serial ATA status */
381 P2DD, 4,
382 , 4,
383 P2IS, 4,
384 Offset(0x22C), /* Port 2 Serial ATA control */
385 P2DI, 4,
386 Offset(0x230), /* Port 2 Serial ATA error */
387 , 16,
388 P2PR, 1,
390 /* Port 3 */
391 Offset(0x2A0), /* Port 3 Task file status */
392 P3ER, 1,
393 , 2,
394 P3DQ, 1,
395 , 3,
396 P3BY, 1,
397 Offset(0x2A8), /* Port 3 Serial ATA status */
398 P3DD, 4,
399 , 4,
400 P3IS, 4,
401 Offset(0x2AC), /* Port 3 Serial ATA control */
402 P3DI, 4,
403 Offset(0x2B0), /* Port 3 Serial ATA error */
404 , 16,
405 P3PR, 1,
406 }
407 }
410 #include "acpi/routing.asl"
412 Scope(\_SB) {
414 Method(OSFL, 0){
416 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
418 if(CondRefOf(\_OSI,Local1))
419 {
420 Store(1, OSVR) /* Assume some form of XP */
421 if (\_OSI("Windows 2006")) /* Vista */
422 {
423 Store(2, OSVR)
424 }
425 } else {
426 If(WCMP(\_OS,"Linux")) {
427 Store(3, OSVR) /* Linux */
428 } Else {
429 Store(4, OSVR) /* Gotta be WinCE */
430 }
431 }
432 Return(OSVR)
433 }
435 Method(_PIC, 0x01, NotSerialized)
436 {
437 If (Arg0)
438 {
439 \_SB.CIRQ()
440 }
441 Store(Arg0, PMOD)
442 }
443 Method(CIRQ, 0x00, NotSerialized){
444 Store(0, PINA)
445 Store(0, PINB)
446 Store(0, PINC)
447 Store(0, PIND)
448 Store(0, PINE)
449 Store(0, PINF)
450 Store(0, PING)
451 Store(0, PINH)
452 }
454 Name(IRQB, ResourceTemplate(){
455 IRQ(Level,ActiveLow,Shared){15}
456 })
458 Name(IRQP, ResourceTemplate(){
459 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
460 })
462 Name(PITF, ResourceTemplate(){
463 IRQ(Level,ActiveLow,Exclusive){9}
464 })
466 Device(INTA) {
467 Name(_HID, EISAID("PNP0C0F"))
468 Name(_UID, 1)
470 Method(_STA, 0) {
471 if (PINA) {
472 Return(0x0B) /* sata is invisible */
473 } else {
474 Return(0x09) /* sata is disabled */
475 }
476 } /* End Method(_SB.INTA._STA) */
478 Method(_DIS ,0) {
479 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
480 Store(0, PINA)
481 } /* End Method(_SB.INTA._DIS) */
483 Method(_PRS ,0) {
484 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
485 Return(IRQP)
486 } /* Method(_SB.INTA._PRS) */
488 Method(_CRS ,0) {
489 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
490 CreateWordField(IRQB, 0x1, IRQN)
491 ShiftLeft(1, PINA, IRQN)
492 Return(IRQB)
493 } /* Method(_SB.INTA._CRS) */
495 Method(_SRS, 1) {
496 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
497 CreateWordField(ARG0, 1, IRQM)
499 /* Use lowest available IRQ */
500 FindSetRightBit(IRQM, Local0)
501 if (Local0) {
502 Decrement(Local0)
503 }
504 Store(Local0, PINA)
505 } /* End Method(_SB.INTA._SRS) */
506 } /* End Device(INTA) */
508 Device(INTB) {
509 Name(_HID, EISAID("PNP0C0F"))
510 Name(_UID, 2)
512 Method(_STA, 0) {
513 if (PINB) {
514 Return(0x0B) /* sata is invisible */
515 } else {
516 Return(0x09) /* sata is disabled */
517 }
518 } /* End Method(_SB.INTB._STA) */
520 Method(_DIS ,0) {
521 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
522 Store(0, PINB)
523 } /* End Method(_SB.INTB._DIS) */
525 Method(_PRS ,0) {
526 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
527 Return(IRQP)
528 } /* Method(_SB.INTB._PRS) */
530 Method(_CRS ,0) {
531 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
532 CreateWordField(IRQB, 0x1, IRQN)
533 ShiftLeft(1, PINB, IRQN)
534 Return(IRQB)
535 } /* Method(_SB.INTB._CRS) */
537 Method(_SRS, 1) {
538 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
539 CreateWordField(ARG0, 1, IRQM)
541 /* Use lowest available IRQ */
542 FindSetRightBit(IRQM, Local0)
543 if (Local0) {
544 Decrement(Local0)
545 }
546 Store(Local0, PINB)
547 } /* End Method(_SB.INTB._SRS) */
548 } /* End Device(INTB) */
550 Device(INTC) {
551 Name(_HID, EISAID("PNP0C0F"))
552 Name(_UID, 3)
554 Method(_STA, 0) {
555 if (PINC) {
556 Return(0x0B) /* sata is invisible */
557 } else {
558 Return(0x09) /* sata is disabled */
559 }
560 } /* End Method(_SB.INTC._STA) */
562 Method(_DIS ,0) {
563 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
564 Store(0, PINC)
565 } /* End Method(_SB.INTC._DIS) */
567 Method(_PRS ,0) {
568 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
569 Return(IRQP)
570 } /* Method(_SB.INTC._PRS) */
572 Method(_CRS ,0) {
573 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
574 CreateWordField(IRQB, 0x1, IRQN)
575 ShiftLeft(1, PINC, IRQN)
576 Return(IRQB)
577 } /* Method(_SB.INTC._CRS) */
579 Method(_SRS, 1) {
580 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
581 CreateWordField(ARG0, 1, IRQM)
583 /* Use lowest available IRQ */
584 FindSetRightBit(IRQM, Local0)
585 if (Local0) {
586 Decrement(Local0)
587 }
588 Store(Local0, PINC)
589 } /* End Method(_SB.INTC._SRS) */
590 } /* End Device(INTC) */
592 Device(INTD) {
593 Name(_HID, EISAID("PNP0C0F"))
594 Name(_UID, 4)
596 Method(_STA, 0) {
597 if (PIND) {
598 Return(0x0B) /* sata is invisible */
599 } else {
600 Return(0x09) /* sata is disabled */
601 }
602 } /* End Method(_SB.INTD._STA) */
604 Method(_DIS ,0) {
605 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
606 Store(0, PIND)
607 } /* End Method(_SB.INTD._DIS) */
609 Method(_PRS ,0) {
610 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
611 Return(IRQP)
612 } /* Method(_SB.INTD._PRS) */
614 Method(_CRS ,0) {
615 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
616 CreateWordField(IRQB, 0x1, IRQN)
617 ShiftLeft(1, PIND, IRQN)
618 Return(IRQB)
619 } /* Method(_SB.INTD._CRS) */
621 Method(_SRS, 1) {
622 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
623 CreateWordField(ARG0, 1, IRQM)
625 /* Use lowest available IRQ */
626 FindSetRightBit(IRQM, Local0)
627 if (Local0) {
628 Decrement(Local0)
629 }
630 Store(Local0, PIND)
631 } /* End Method(_SB.INTD._SRS) */
632 } /* End Device(INTD) */
634 Device(INTE) {
635 Name(_HID, EISAID("PNP0C0F"))
636 Name(_UID, 5)
638 Method(_STA, 0) {
639 if (PINE) {
640 Return(0x0B) /* sata is invisible */
641 } else {
642 Return(0x09) /* sata is disabled */
643 }
644 } /* End Method(_SB.INTE._STA) */
646 Method(_DIS ,0) {
647 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
648 Store(0, PINE)
649 } /* End Method(_SB.INTE._DIS) */
651 Method(_PRS ,0) {
652 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
653 Return(IRQP)
654 } /* Method(_SB.INTE._PRS) */
656 Method(_CRS ,0) {
657 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
658 CreateWordField(IRQB, 0x1, IRQN)
659 ShiftLeft(1, PINE, IRQN)
660 Return(IRQB)
661 } /* Method(_SB.INTE._CRS) */
663 Method(_SRS, 1) {
664 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
665 CreateWordField(ARG0, 1, IRQM)
667 /* Use lowest available IRQ */
668 FindSetRightBit(IRQM, Local0)
669 if (Local0) {
670 Decrement(Local0)
671 }
672 Store(Local0, PINE)
673 } /* End Method(_SB.INTE._SRS) */
674 } /* End Device(INTE) */
676 Device(INTF) {
677 Name(_HID, EISAID("PNP0C0F"))
678 Name(_UID, 6)
680 Method(_STA, 0) {
681 if (PINF) {
682 Return(0x0B) /* sata is invisible */
683 } else {
684 Return(0x09) /* sata is disabled */
685 }
686 } /* End Method(_SB.INTF._STA) */
688 Method(_DIS ,0) {
689 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
690 Store(0, PINF)
691 } /* End Method(_SB.INTF._DIS) */
693 Method(_PRS ,0) {
694 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
695 Return(PITF)
696 } /* Method(_SB.INTF._PRS) */
698 Method(_CRS ,0) {
699 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
700 CreateWordField(IRQB, 0x1, IRQN)
701 ShiftLeft(1, PINF, IRQN)
702 Return(IRQB)
703 } /* Method(_SB.INTF._CRS) */
705 Method(_SRS, 1) {
706 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
707 CreateWordField(ARG0, 1, IRQM)
709 /* Use lowest available IRQ */
710 FindSetRightBit(IRQM, Local0)
711 if (Local0) {
712 Decrement(Local0)
713 }
714 Store(Local0, PINF)
715 } /* End Method(_SB.INTF._SRS) */
716 } /* End Device(INTF) */
718 Device(INTG) {
719 Name(_HID, EISAID("PNP0C0F"))
720 Name(_UID, 7)
722 Method(_STA, 0) {
723 if (PING) {
724 Return(0x0B) /* sata is invisible */
725 } else {
726 Return(0x09) /* sata is disabled */
727 }
728 } /* End Method(_SB.INTG._STA) */
730 Method(_DIS ,0) {
731 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
732 Store(0, PING)
733 } /* End Method(_SB.INTG._DIS) */
735 Method(_PRS ,0) {
736 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
737 Return(IRQP)
738 } /* Method(_SB.INTG._CRS) */
740 Method(_CRS ,0) {
741 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
742 CreateWordField(IRQB, 0x1, IRQN)
743 ShiftLeft(1, PING, IRQN)
744 Return(IRQB)
745 } /* Method(_SB.INTG._CRS) */
747 Method(_SRS, 1) {
748 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
749 CreateWordField(ARG0, 1, IRQM)
751 /* Use lowest available IRQ */
752 FindSetRightBit(IRQM, Local0)
753 if (Local0) {
754 Decrement(Local0)
755 }
756 Store(Local0, PING)
757 } /* End Method(_SB.INTG._SRS) */
758 } /* End Device(INTG) */
760 Device(INTH) {
761 Name(_HID, EISAID("PNP0C0F"))
762 Name(_UID, 8)
764 Method(_STA, 0) {
765 if (PINH) {
766 Return(0x0B) /* sata is invisible */
767 } else {
768 Return(0x09) /* sata is disabled */
769 }
770 } /* End Method(_SB.INTH._STA) */
772 Method(_DIS ,0) {
773 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
774 Store(0, PINH)
775 } /* End Method(_SB.INTH._DIS) */
777 Method(_PRS ,0) {
778 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
779 Return(IRQP)
780 } /* Method(_SB.INTH._CRS) */
782 Method(_CRS ,0) {
783 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
784 CreateWordField(IRQB, 0x1, IRQN)
785 ShiftLeft(1, PINH, IRQN)
786 Return(IRQB)
787 } /* Method(_SB.INTH._CRS) */
789 Method(_SRS, 1) {
790 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
791 CreateWordField(ARG0, 1, IRQM)
793 /* Use lowest available IRQ */
794 FindSetRightBit(IRQM, Local0)
795 if (Local0) {
796 Decrement(Local0)
797 }
798 Store(Local0, PINH)
799 } /* End Method(_SB.INTH._SRS) */
800 } /* End Device(INTH) */
802 } /* End Scope(_SB) */
805 /* Supported sleep states: */
806 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
808 If (LAnd(SSFG, 0x01)) {
809 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
810 }
811 If (LAnd(SSFG, 0x02)) {
812 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
813 }
814 If (LAnd(SSFG, 0x04)) {
815 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
816 }
817 If (LAnd(SSFG, 0x08)) {
818 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
819 }
821 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
823 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
824 Name(CSMS, 0) /* Current System State */
826 /* Wake status package */
827 Name(WKST,Package(){Zero, Zero})
829 /*
830 * \_PTS - Prepare to Sleep method
831 *
832 * Entry:
833 * Arg0=The value of the sleeping state S1=1, S2=2, etc
834 *
835 * Exit:
836 * -none-
837 *
838 * The _PTS control method is executed at the beginning of the sleep process
839 * for S1-S5. The sleeping value is passed to the _PTS control method. This
840 * control method may be executed a relatively long time before entering the
841 * sleep state and the OS may abort the operation without notification to
842 * the ACPI driver. This method cannot modify the configuration or power
843 * state of any device in the system.
844 */
845 Method(\_PTS, 1) {
846 /* DBGO("\\_PTS\n") */
847 /* DBGO("From S0 to S") */
848 /* DBGO(Arg0) */
849 /* DBGO("\n") */
851 /* Don't allow PCIRST# to reset USB */
852 if (LEqual(Arg0,3)){
853 Store(0,URRE)
854 }
856 /* Clear sleep SMI status flag and enable sleep SMI trap. */
857 /*Store(One, CSSM)
858 Store(One, SSEN)*/
860 /* On older chips, clear PciExpWakeDisEn */
861 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
862 * Store(0,\_SB.PWDE)
863 *}
864 */
866 /* Clear wake status structure. */
867 Store(0, Index(WKST,0))
868 Store(0, Index(WKST,1))
869 \_SB.PCI0.SIOS (Arg0)
870 } /* End Method(\_PTS) */
872 /*
873 * The following method results in a "not a valid reserved NameSeg"
874 * warning so I have commented it out for the duration. It isn't
875 * used, so it could be removed.
876 *
877 *
878 * \_GTS OEM Going To Sleep method
879 *
880 * Entry:
881 * Arg0=The value of the sleeping state S1=1, S2=2
882 *
883 * Exit:
884 * -none-
885 *
886 * Method(\_GTS, 1) {
887 * DBGO("\\_GTS\n")
888 * DBGO("From S0 to S")
889 * DBGO(Arg0)
890 * DBGO("\n")
891 * }
892 */
894 /*
895 * \_BFS OEM Back From Sleep method
896 *
897 * Entry:
898 * Arg0=The value of the sleeping state S1=1, S2=2
899 *
900 * Exit:
901 * -none-
902 */
903 Method(\_BFS, 1) {
904 /* DBGO("\\_BFS\n") */
905 /* DBGO("From S") */
906 /* DBGO(Arg0) */
907 /* DBGO(" to S0\n") */
908 }
910 /*
911 * \_WAK System Wake method
912 *
913 * Entry:
914 * Arg0=The value of the sleeping state S1=1, S2=2
915 *
916 * Exit:
917 * Return package of 2 DWords
918 * Dword 1 - Status
919 * 0x00000000 wake succeeded
920 * 0x00000001 Wake was signaled but failed due to lack of power
921 * 0x00000002 Wake was signaled but failed due to thermal condition
922 * Dword 2 - Power Supply state
923 * if non-zero the effective S-state the power supply entered
924 */
925 Method(\_WAK, 1) {
926 /* DBGO("\\_WAK\n") */
927 /* DBGO("From S") */
928 /* DBGO(Arg0) */
929 /* DBGO(" to S0\n") */
931 /* Re-enable HPET */
932 Store(1,HPDE)
934 /* Restore PCIRST# so it resets USB */
935 if (LEqual(Arg0,3)){
936 Store(1,URRE)
937 }
939 /* Arbitrarily clear PciExpWakeStatus */
940 Store(PWST, PWST)
942 /* if(DeRefOf(Index(WKST,0))) {
943 * Store(0, Index(WKST,1))
944 * } else {
945 * Store(Arg0, Index(WKST,1))
946 * }
947 */
948 \_SB.PCI0.SIOW (Arg0)
949 Return(WKST)
950 } /* End Method(\_WAK) */
952 Scope(\_GPE) { /* Start Scope GPE */
953 /* General event 0 */
954 /* Method(_L00) {
955 * DBGO("\\_GPE\\_L00\n")
956 * }
957 */
959 /* General event 1 */
960 /* Method(_L01) {
961 * DBGO("\\_GPE\\_L00\n")
962 * }
963 */
965 /* General event 2 */
966 /* Method(_L02) {
967 * DBGO("\\_GPE\\_L00\n")
968 * }
969 */
971 /* General event 3 */
972 Method(_L03) {
973 /* DBGO("\\_GPE\\_L00\n") */
974 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
975 }
977 /* General event 4 */
978 /* Method(_L04) {
979 * DBGO("\\_GPE\\_L00\n")
980 * }
981 */
983 /* General event 5 */
984 /* Method(_L05) {
985 * DBGO("\\_GPE\\_L00\n")
986 * }
987 */
989 /* General event 6 - Used for GPM6, moved to USB.asl */
990 /* Method(_L06) {
991 * DBGO("\\_GPE\\_L00\n")
992 * }
993 */
995 /* General event 7 - Used for GPM7, moved to USB.asl */
996 /* Method(_L07) {
997 * DBGO("\\_GPE\\_L07\n")
998 * }
999 */
1001 /* Legacy PM event */
1002 Method(_L08) {
1003 /* DBGO("\\_GPE\\_L08\n") */
1004 }
1006 /* Temp warning (TWarn) event */
1007 Method(_L09) {
1008 /* DBGO("\\_GPE\\_L09\n") */
1009 Notify (\_TZ.TZ00, 0x80)
1010 }
1012 /* Reserved */
1013 /* Method(_L0A) {
1014 * DBGO("\\_GPE\\_L0A\n")
1015 * }
1016 */
1018 /* USB controller PME# */
1019 Method(_L0B) {
1020 /* DBGO("\\_GPE\\_L0B\n") */
1021 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1022 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1023 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1024 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1025 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1026 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1027 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1028 }
1030 /* AC97 controller PME# */
1031 /* Method(_L0C) {
1032 * DBGO("\\_GPE\\_L0C\n")
1033 * }
1034 */
1036 /* OtherTherm PME# */
1037 /* Method(_L0D) {
1038 * DBGO("\\_GPE\\_L0D\n")
1039 * }
1040 */
1042 /* GPM9 SCI event - Moved to USB.asl */
1043 /* Method(_L0E) {
1044 * DBGO("\\_GPE\\_L0E\n")
1045 * }
1046 */
1048 /* PCIe HotPlug event */
1049 /* Method(_L0F) {
1050 * DBGO("\\_GPE\\_L0F\n")
1051 * }
1052 */
1054 /* ExtEvent0 SCI event */
1055 Method(_L10) {
1056 /* DBGO("\\_GPE\\_L10\n") */
1057 }
1060 /* ExtEvent1 SCI event */
1061 Method(_L11) {
1062 /* DBGO("\\_GPE\\_L11\n") */
1063 }
1065 /* PCIe PME# event */
1066 /* Method(_L12) {
1067 * DBGO("\\_GPE\\_L12\n")
1068 * }
1069 */
1071 /* GPM0 SCI event - Moved to USB.asl */
1072 /* Method(_L13) {
1073 * DBGO("\\_GPE\\_L13\n")
1074 * }
1075 */
1077 /* GPM1 SCI event - Moved to USB.asl */
1078 /* Method(_L14) {
1079 * DBGO("\\_GPE\\_L14\n")
1080 * }
1081 */
1083 /* GPM2 SCI event - Moved to USB.asl */
1084 /* Method(_L15) {
1085 * DBGO("\\_GPE\\_L15\n")
1086 * }
1087 */
1089 /* GPM3 SCI event - Moved to USB.asl */
1090 /* Method(_L16) {
1091 * DBGO("\\_GPE\\_L16\n")
1092 * }
1093 */
1095 /* GPM8 SCI event - Moved to USB.asl */
1096 /* Method(_L17) {
1097 * DBGO("\\_GPE\\_L17\n")
1098 * }
1099 */
1101 /* GPIO0 or GEvent8 event */
1102 Method(_L18) {
1103 /* DBGO("\\_GPE\\_L18\n") */
1104 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1105 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1106 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1107 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1108 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1109 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1110 }
1112 /* GPM4 SCI event - Moved to USB.asl */
1113 /* Method(_L19) {
1114 * DBGO("\\_GPE\\_L19\n")
1115 * }
1116 */
1118 /* GPM5 SCI event - Moved to USB.asl */
1119 /* Method(_L1A) {
1120 * DBGO("\\_GPE\\_L1A\n")
1121 * }
1122 */
1124 /* Azalia SCI event */
1125 Method(_L1B) {
1126 /* DBGO("\\_GPE\\_L1B\n") */
1127 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1128 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1129 }
1131 /* GPM6 SCI event - Reassigned to _L06 */
1132 /* Method(_L1C) {
1133 * DBGO("\\_GPE\\_L1C\n")
1134 * }
1135 */
1137 /* GPM7 SCI event - Reassigned to _L07 */
1138 /* Method(_L1D) {
1139 * DBGO("\\_GPE\\_L1D\n")
1140 * }
1141 */
1143 /* GPIO2 or GPIO66 SCI event */
1144 /* Method(_L1E) {
1145 * DBGO("\\_GPE\\_L1E\n")
1146 * }
1147 */
1149 /* SATA SCI event - Moved to sata.asl */
1150 /* Method(_L1F) {
1151 * DBGO("\\_GPE\\_L1F\n")
1152 * }
1153 */
1155 } /* End Scope GPE */
1157 #include "acpi/usb.asl"
1159 /* South Bridge */
1160 Scope(\_SB) { /* Start \_SB scope */
1161 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1163 /* _SB.PCI0 */
1164 /* Note: Only need HID on Primary Bus */
1165 Device(PCI0) {
1166 External (TOM1)
1167 External (TOM2)
1168 Name(_HID, EISAID("PNP0A03"))
1169 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1170 Method(_BBN, 0) { /* Bus number = 0 */
1171 Return(0)
1172 }
1173 Method(_STA, 0) {
1174 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1175 Return(0x0B) /* Status is visible */
1176 }
1178 Method(_PRT,0) {
1179 If(PMOD){ Return(APR0) } /* APIC mode */
1180 Return (PR0) /* PIC Mode */
1181 } /* end _PRT */
1183 /* Describe the Northbridge devices */
1184 Device(AMRT) {
1185 Name(_ADR, 0x00000000)
1186 } /* end AMRT */
1188 /* The internal GFX bridge */
1189 Device(AGPB) {
1190 Name(_ADR, 0x00010000)
1191 Name(_PRW, Package() {0x18, 4})
1192 Method(_PRT,0) {
1193 Return (APR1)
1194 }
1195 } /* end AGPB */
1197 /* The external GFX bridge */
1198 Device(PBR2) {
1199 Name(_ADR, 0x00020000)
1200 Name(_PRW, Package() {0x18, 4})
1201 Method(_PRT,0) {
1202 If(PMOD){ Return(APS2) } /* APIC mode */
1203 Return (PS2) /* PIC Mode */
1204 } /* end _PRT */
1205 } /* end PBR2 */
1207 /* Dev3 is also an external GFX bridge, not used in Herring */
1209 Device(PBR4) {
1210 Name(_ADR, 0x00040000)
1211 Name(_PRW, Package() {0x18, 4})
1212 Method(_PRT,0) {
1213 If(PMOD){ Return(APS4) } /* APIC mode */
1214 Return (PS4) /* PIC Mode */
1215 } /* end _PRT */
1216 } /* end PBR4 */
1218 Device(PBR5) {
1219 Name(_ADR, 0x00050000)
1220 Name(_PRW, Package() {0x18, 4})
1221 Method(_PRT,0) {
1222 If(PMOD){ Return(APS5) } /* APIC mode */
1223 Return (PS5) /* PIC Mode */
1224 } /* end _PRT */
1225 } /* end PBR5 */
1227 Device(PBR6) {
1228 Name(_ADR, 0x00060000)
1229 Name(_PRW, Package() {0x18, 4})
1230 Method(_PRT,0) {
1231 If(PMOD){ Return(APS6) } /* APIC mode */
1232 Return (PS6) /* PIC Mode */
1233 } /* end _PRT */
1234 } /* end PBR6 */
1236 /* The onboard EtherNet chip */
1237 Device(PBR7) {
1238 Name(_ADR, 0x00070000)
1239 Name(_PRW, Package() {0x18, 4})
1240 Method(_PRT,0) {
1241 If(PMOD){ Return(APS7) } /* APIC mode */
1242 Return (PS7) /* PIC Mode */
1243 } /* end _PRT */
1244 } /* end PBR7 */
1246 /* GPP */
1247 Device(PBR9) {
1248 Name(_ADR, 0x00090000)
1249 Name(_PRW, Package() {0x18, 4})
1250 Method(_PRT,0) {
1251 If(PMOD){ Return(APS9) } /* APIC mode */
1252 Return (PS9) /* PIC Mode */
1253 } /* end _PRT */
1254 } /* end PBR9 */
1256 Device(PBRa) {
1257 Name(_ADR, 0x000A0000)
1258 Name(_PRW, Package() {0x18, 4})
1259 Method(_PRT,0) {
1260 If(PMOD){ Return(APSa) } /* APIC mode */
1261 Return (PSa) /* PIC Mode */
1262 } /* end _PRT */
1263 } /* end PBRa */
1266 /* PCI slot 1, 2, 3 */
1267 Device(PIBR) {
1268 Name(_ADR, 0x00140004)
1269 Name(_PRW, Package() {0x18, 4})
1271 Method(_PRT, 0) {
1272 Return (PCIB)
1273 }
1274 }
1276 /* Describe the Southbridge devices */
1277 Device(STCR) {
1278 Name(_ADR, 0x00110000)
1279 #include "acpi/sata.asl"
1280 } /* end STCR */
1282 Device(UOH1) {
1283 Name(_ADR, 0x00130000)
1284 Name(_PRW, Package() {0x0B, 3})
1285 } /* end UOH1 */
1287 Device(UOH2) {
1288 Name(_ADR, 0x00130001)
1289 Name(_PRW, Package() {0x0B, 3})
1290 } /* end UOH2 */
1292 Device(UOH3) {
1293 Name(_ADR, 0x00130002)
1294 Name(_PRW, Package() {0x0B, 3})
1295 } /* end UOH3 */
1297 Device(UOH4) {
1298 Name(_ADR, 0x00130003)
1299 Name(_PRW, Package() {0x0B, 3})
1300 } /* end UOH4 */
1302 Device(UOH5) {
1303 Name(_ADR, 0x00130004)
1304 Name(_PRW, Package() {0x0B, 3})
1305 } /* end UOH5 */
1307 Device(UEH1) {
1308 Name(_ADR, 0x00130005)
1309 Name(_PRW, Package() {0x0B, 3})
1310 } /* end UEH1 */
1312 Device(SBUS) {
1313 Name(_ADR, 0x00140000)
1314 } /* end SBUS */
1316 /* Primary (and only) IDE channel */
1317 Device(IDEC) {
1318 Name(_ADR, 0x00140001)
1319 #include "acpi/ide.asl"
1320 } /* end IDEC */
1322 Device(AZHD) {
1323 Name(_ADR, 0x00140002)
1324 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1325 Field(AZPD, AnyAcc, NoLock, Preserve) {
1326 offset (0x42),
1327 NSDI, 1,
1328 NSDO, 1,
1329 NSEN, 1,
1330 offset (0x44),
1331 IPCR, 4,
1332 offset (0x54),
1333 PWST, 2,
1334 , 6,
1335 PMEB, 1,
1336 , 6,
1337 PMST, 1,
1338 offset (0x62),
1339 MMCR, 1,
1340 offset (0x64),
1341 MMLA, 32,
1342 offset (0x68),
1343 MMHA, 32,
1344 offset (0x6C),
1345 MMDT, 16,
1346 }
1348 Method(_INI) {
1349 If(LEqual(OSVR,3)){ /* If we are running Linux */
1350 Store(zero, NSEN)
1351 Store(one, NSDO)
1352 Store(one, NSDI)
1353 }
1354 }
1355 } /* end AZHD */
1357 Device(LIBR) {
1358 Name(_ADR, 0x00140003)
1359 /* Method(_INI) {
1360 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1361 } */ /* End Method(_SB.SBRDG._INI) */
1363 /* Real Time Clock Device */
1364 Device(RTC0) {
1365 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1366 Name(_CRS, ResourceTemplate() {
1367 IRQNoFlags(){8}
1368 IO(Decode16,0x0070, 0x0070, 0, 2)
1369 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1370 })
1371 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1373 Device(TMR) { /* Timer */
1374 Name(_HID,EISAID("PNP0100")) /* System Timer */
1375 Name(_CRS, ResourceTemplate() {
1376 IRQNoFlags(){0}
1377 IO(Decode16, 0x0040, 0x0040, 0, 4)
1378 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1379 })
1380 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1382 Device(SPKR) { /* Speaker */
1383 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1384 Name(_CRS, ResourceTemplate() {
1385 IO(Decode16, 0x0061, 0x0061, 0, 1)
1386 })
1387 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1389 Device(PIC) {
1390 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1391 Name(_CRS, ResourceTemplate() {
1392 IRQNoFlags(){2}
1393 IO(Decode16,0x0020, 0x0020, 0, 2)
1394 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1395 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1396 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1397 })
1398 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1400 Device(MAD) { /* 8257 DMA */
1401 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1402 Name(_CRS, ResourceTemplate() {
1403 DMA(Compatibility,BusMaster,Transfer8){4}
1404 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1405 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1406 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1407 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1408 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1409 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1410 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1411 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1413 Device(COPR) {
1414 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1415 Name(_CRS, ResourceTemplate() {
1416 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1417 IRQNoFlags(){13}
1418 })
1419 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1420 #if 0 /* defined by HPET table? */
1421 Device(HPTM) {
1422 Name(_HID,EISAID("PNP0103"))
1423 Name(CRS,ResourceTemplate() {
1424 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1425 })
1426 Method(_STA, 0) {
1427 Return(0x0F) /* sata is visible */
1428 }
1429 Method(_CRS, 0) {
1430 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1431 Store(HPBA, HPBA)
1432 Return(CRS)
1433 }
1434 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1435 #endif
1436 } /* end LIBR */
1438 Device(HPBR) {
1439 Name(_ADR, 0x00140004)
1440 } /* end HostPciBr */
1442 Device(ACAD) {
1443 Name(_ADR, 0x00140005)
1444 } /* end Ac97audio */
1446 Device(ACMD) {
1447 Name(_ADR, 0x00140006)
1448 } /* end Ac97modem */
1450 /* ITE8718 Support */
1451 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1452 Field (IOID, ByteAcc, NoLock, Preserve)
1453 {
1454 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1455 }
1457 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1458 {
1459 Offset (0x07),
1460 LDN, 8, /* Logical Device Number */
1461 Offset (0x20),
1462 CID1, 8, /* Chip ID Byte 1, 0x87 */
1463 CID2, 8, /* Chip ID Byte 2, 0x12 */
1464 Offset (0x30),
1465 ACTR, 8, /* Function activate */
1466 Offset (0xF0),
1467 APC0, 8, /* APC/PME Event Enable Register */
1468 APC1, 8, /* APC/PME Status Register */
1469 APC2, 8, /* APC/PME Control Register 1 */
1470 APC3, 8, /* Environment Controller Special Configuration Register */
1471 APC4, 8 /* APC/PME Control Register 2 */
1472 }
1474 /* Enter the 8718 MB PnP Mode */
1475 Method (EPNP)
1476 {
1477 Store(0x87, SIOI)
1478 Store(0x01, SIOI)
1479 Store(0x55, SIOI)
1480 Store(0x55, SIOI) /* 8718 magic number */
1481 }
1482 /* Exit the 8718 MB PnP Mode */
1483 Method (XPNP)
1484 {
1485 Store (0x02, SIOI)
1486 Store (0x02, SIOD)
1487 }
1488 /*
1489 * Keyboard PME is routed to SB700 Gevent3. We can wake
1490 * up the system by pressing the key.
1491 */
1492 Method (SIOS, 1)
1493 {
1494 /* We only enable KBD PME for S5. */
1495 If (LLess (Arg0, 0x05))
1496 {
1497 EPNP()
1498 /* DBGO("8718F\n") */
1500 Store (0x4, LDN)
1501 Store (One, ACTR) /* Enable EC */
1502 /*
1503 Store (0x4, LDN)
1504 Store (0x04, APC4)
1505 */ /* falling edge. which mode? Not sure. */
1507 Store (0x4, LDN)
1508 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1509 Store (0x4, LDN)
1510 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1512 XPNP()
1513 }
1514 }
1515 Method (SIOW, 1)
1516 {
1517 EPNP()
1518 Store (0x4, LDN)
1519 Store (Zero, APC0) /* disable keyboard PME */
1520 Store (0x4, LDN)
1521 Store (0xFF, APC1) /* clear keyboard PME status */
1522 XPNP()
1523 }
1525 Name(CRES, ResourceTemplate() {
1526 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1528 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1529 0x0000, /* address granularity */
1530 0x0000, /* range minimum */
1531 0x0CF7, /* range maximum */
1532 0x0000, /* translation */
1533 0x0CF8 /* length */
1534 )
1536 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1537 0x0000, /* address granularity */
1538 0x0D00, /* range minimum */
1539 0xFFFF, /* range maximum */
1540 0x0000, /* translation */
1541 0xF300 /* length */
1542 )
1544 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1545 #if 0
1546 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1547 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1548 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1550 /* DRAM Memory from 1MB to TopMem */
1551 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1553 /* BIOS space just below 4GB */
1554 DWORDMemory(
1555 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1556 0x00, /* Granularity */
1557 0x00000000, /* Min */
1558 0x00000000, /* Max */
1559 0x00000000, /* Translation */
1560 0x00000001, /* Max-Min, RLEN */
1561 ,,
1562 PCBM
1563 )
1565 /* DRAM memory from 4GB to TopMem2 */
1566 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1567 0x00000000, /* Granularity */
1568 0x00000000, /* Min */
1569 0x00000000, /* Max */
1570 0x00000000, /* Translation */
1571 0x00000001, /* Max-Min, RLEN */
1572 ,,
1573 DMHI
1574 )
1576 /* BIOS space just below 16EB */
1577 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1578 0x00000000, /* Granularity */
1579 0x00000000, /* Min */
1580 0x00000000, /* Max */
1581 0x00000000, /* Translation */
1582 0x00000001, /* Max-Min, RLEN */
1583 ,,
1584 PEBM
1585 )
1586 #endif
1587 /* memory space for PCI BARs below 4GB */
1588 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1589 }) /* End Name(_SB.PCI0.CRES) */
1591 Method(_CRS, 0) {
1592 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1593 #if 0
1594 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1595 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1596 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1597 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1598 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1599 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1601 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1602 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1603 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1604 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1606 If(LGreater(LOMH, 0xC0000)){
1607 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1608 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1609 }
1611 /* Set size of memory from 1MB to TopMem */
1612 Subtract(TOM1, 0x100000, DMLL)
1614 /*
1615 * If(LNotEqual(TOM2, 0x00000000)){
1616 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1617 * Subtract(TOM2, 0x100000000, DMHL)
1618 * }
1619 */
1621 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1622 If(LEqual(TOM2, 0x00000000)){
1623 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1624 Store(PBLN,PBML)
1625 }
1626 Else { /* Otherwise, put the BIOS just below 16EB */
1627 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1628 Store(PBLN,EBML)
1629 }
1630 #endif
1631 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1632 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1633 /*
1634 * Declare memory between TOM1 and 4GB as available
1635 * for PCI MMIO.
1636 * Use ShiftLeft to avoid 64bit constant (for XP).
1637 * This will work even if the OS does 32bit arithmetic, as
1638 * 32bit (0x00000000 - TOM1) will wrap and give the same
1639 * result as 64bit (0x100000000 - TOM1).
1640 */
1641 Store(TOM1, MM1B)
1642 ShiftLeft(0x10000000, 4, Local0)
1643 Subtract(Local0, TOM1, Local0)
1644 Store(Local0, MM1L)
1646 Return(CRES) /* note to change the Name buffer */
1647 } /* end of Method(_SB.PCI0._CRS) */
1649 /*
1650 *
1651 * FIRST METHOD CALLED UPON BOOT
1652 *
1653 * 1. If debugging, print current OS and ACPI interpreter.
1654 * 2. Get PCI Interrupt routing from ACPI VSM, this
1655 * value is based on user choice in BIOS setup.
1656 */
1657 Method(_INI, 0) {
1658 /* DBGO("\\_SB\\_INI\n") */
1659 /* DBGO(" DSDT.ASL code from ") */
1660 /* DBGO(__DATE__) */
1661 /* DBGO(" ") */
1662 /* DBGO(__TIME__) */
1663 /* DBGO("\n Sleep states supported: ") */
1664 /* DBGO("\n") */
1665 /* DBGO(" \\_OS=") */
1666 /* DBGO(\_OS) */
1667 /* DBGO("\n \\_REV=") */
1668 /* DBGO(\_REV) */
1669 /* DBGO("\n") */
1671 /* Determine the OS we're running on */
1672 OSFL()
1674 /* On older chips, clear PciExpWakeDisEn */
1675 /*if (LLessEqual(\SBRI, 0x13)) {
1676 * Store(0,\PWDE)
1677 * }
1678 */
1679 } /* End Method(_SB._INI) */
1680 } /* End Device(PCI0) */
1682 Device(PWRB) { /* Start Power button device */
1683 Name(_HID, EISAID("PNP0C0C"))
1684 Name(_UID, 0xAA)
1685 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1686 Name(_STA, 0x0B) /* sata is invisible */
1687 }
1688 } /* End \_SB scope */
1690 Scope(\_SI) {
1691 Method(_SST, 1) {
1692 /* DBGO("\\_SI\\_SST\n") */
1693 /* DBGO(" New Indicator state: ") */
1694 /* DBGO(Arg0) */
1695 /* DBGO("\n") */
1696 }
1697 } /* End Scope SI */
1699 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1701 /* THERMAL */
1702 Scope(\_TZ) {
1703 Name (KELV, 2732)
1704 Name (THOT, 800)
1705 Name (TCRT, 850)
1707 ThermalZone(TZ00) {
1708 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1709 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1710 Return(Add(0, 2730))
1711 }
1712 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1713 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1714 Return(Package() {\_TZ.TZ00.FAN0})
1715 }
1716 Device (FAN0) {
1717 Name(_HID, EISAID("PNP0C0B"))
1718 Name(_PR0, Package() {PFN0})
1719 }
1721 PowerResource(PFN0,0,0) {
1722 Method(_STA) {
1723 Store(0xF,Local0)
1724 Return(Local0)
1725 }
1726 Method(_ON) {
1727 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1728 }
1729 Method(_OFF) {
1730 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1731 }
1732 }
1734 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1735 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1736 Return (Add (THOT, KELV))
1737 }
1738 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1739 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1740 Return (Add (TCRT, KELV))
1741 }
1742 Method(_TMP,0) { /* return current temp of this zone */
1743 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1744 If (LGreater (Local0, 0x10)) {
1745 Store (Local0, Local1)
1746 }
1747 Else {
1748 Add (Local0, THOT, Local0)
1749 Return (Add (400, KELV))
1750 }
1752 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1753 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1754 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1755 If (LGreater (Local0, 0x10)) {
1756 If (LGreater (Local0, Local1)) {
1757 Store (Local0, Local1)
1758 }
1760 Multiply (Local1, 10, Local1)
1761 Return (Add (Local1, KELV))
1762 }
1763 Else {
1764 Add (Local0, THOT, Local0)
1765 Return (Add (400 , KELV))
1766 }
1767 } /* end of _TMP */
1768 } /* end of TZ00 */
1769 }
1770 }
1771 /* End of ASL file */