src/mainboard/amd/inagua/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* DefinitionBlock Statement */
  17 DefinitionBlock (
  18         "DSDT.AML",     /* Output filename */
  19         "DSDT",         /* Signature */
  20         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  21         "AMD   ",       /* OEMID */
  22         "COREBOOT",     /* TABLE ID */
  23         0x00010001      /* OEM Revision */
  24         )
  25 {       /* Start of ASL file */
  26         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  27
  28         #include "acpi/mainboard.asl"
  29
  30         #include <cpu/amd/agesa/family14/acpi/cpu.asl>
  31
  32         #include "acpi/routing.asl"
  33
  34         Scope(\_SB) {
  35                 /* global utility methods expected within the \_SB scope */
  36                 #include <arch/x86/acpi/globutil.asl>
  37
  38                 Device(PCI0) {
  39
  40                         /* Describe the AMD Northbridge */
  41                         #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
  42
  43                         /* Describe the AMD Fusion Controller Hub Southbridge */
  44                         #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
  45
  46                         /* Primary (and only) IDE channel */
  47                         Device(IDEC) {
  48                                 Name(_ADR, 0x00140001)
  49                                 #include "acpi/ide.asl"
  50                         } /* end IDEC */
  51
  52                 }
  53         }   /* End Scope(_SB)  */
  54
  55         /* Contains the supported sleep states for this chipset */
  56         #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
  57
  58         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  59         #include "acpi/sleep.asl"
  60
  61         #include "acpi/gpe.asl"
  62 }
  63 /* End of ASL file */