src/mainboard/amd/inagua/PlatformGnbPcieComplex.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
  17 #define _PLATFORM_GNB_PCIE_COMPLEX_H
  18
  19 #include "Porting.h"
  20 #include "AGESA.h"
  21 #include "amdlib.h"
  22
  23 //GNB GPP Port4
  24 #define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
  25 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
  26 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
  27 #define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  28 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  29 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
  30
  31 //GNB GPP Port5
  32 #define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
  33 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
  34 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
  35 #define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  36 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  37 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
  38
  39 //GNB GPP Port6
  40 #define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
  41 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
  42 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
  43 #define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  44 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  45 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
  46
  47 //GNB GPP Port7
  48 #define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
  49 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
  50 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
  51 #define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  52 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  53 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
  54
  55 //GNB GPP Port8
  56 #define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
  57 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
  58 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
  59 #define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
  60 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
  61 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
  62
  63 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H