src/mainboard/amd/dinar/BiosCallOuts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include "amdlib.h"
  18 #include <northbridge/amd/agesa/agesawrapper.h>
  19 #include <northbridge/amd/agesa/BiosCallOuts.h>
  20 #include "Ids.h"
  21 #include "OptionsIds.h"
  22 #include "heapManager.h"
  23 #include "SB700.h"
  24 #include "OEM.h"                /* SMBUS0_BASE_ADDRESS */
  25 #include <stdlib.h>
  26
  27 #include <southbridge/amd/cimx/sb700/smbus_spd.h>
  28
  29 #ifdef __PRE_RAM__
  30 /* This define is used when selecting the appropriate socket for the SPD read
  31  * because this is a multi-socket design.
  32  */
  33 #define LTC4305_SMBUS_ADDR    (0x94)
  34
  35 static void select_socket(UINT8 socket_id)
  36 {
  37         AMD_CONFIG_PARAMS StdHeader;
  38         UINT32            PciData32;
  39         UINT8             PciData8;
  40         PCI_ADDR          PciAddress;
  41
  42         /* Set SMBus MMIO. */
  43         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
  44         PciData32 = (SMBUS0_BASE_ADDRESS & 0xFFFFFFF0) | BIT0;
  45         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
  46
  47         /* Enable SMBus MMIO. */
  48         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
  49         LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
  50         PciData8 |= BIT0;
  51         LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
  52
  53         switch (socket_id) {
  54         case 0:
  55                 /* Switch onto the First CPU Socket SMBus */
  56                 writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x80, 0x03);
  57                 break;
  58         case 1:
  59                 /* Switch onto the Second CPU Socket SMBus */
  60                 writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x40, 0x03);
  61                 break;
  62         default:
  63                 /* Switch off two CPU Sockets SMBus */
  64                 writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
  65                 break;
  66         }
  67 }
  68
  69 static void restore_socket(void)
  70 {
  71         /* Switch off two CPU Sockets SMBus */
  72         writeSmbusByte(SMBUS0_BASE_ADDRESS, LTC4305_SMBUS_ADDR, 0x00, 0x03);
  73 }
  74 #endif
  75
  76 static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr);
  77
  78 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
  79 {
  80         {AGESA_DO_RESET,                        agesa_Reset },
  81         {AGESA_READ_SPD,                        board_ReadSpd },
  82         {AGESA_READ_SPD_RECOVERY,               agesa_NoopUnsupported },
  83         {AGESA_RUNFUNC_ONAP,                    agesa_RunFuncOnAp },
  84         {AGESA_GNB_PCIE_SLOT_RESET,             agesa_NoopSuccess },
  85         {AGESA_GET_IDS_INIT_DATA,               agesa_EmptyIdsInitData },
  86         {AGESA_HOOKBEFORE_DRAM_INIT,            agesa_NoopSuccess },
  87         {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,   agesa_NoopSuccess },
  88         {AGESA_HOOKBEFORE_DQS_TRAINING,         agesa_NoopSuccess },
  89         {AGESA_HOOKBEFORE_EXIT_SELF_REF,        agesa_NoopSuccess },
  90 };
  91 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
  92
  93
  94 static AGESA_STATUS board_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
  95 {
  96         AGESA_STATUS Status;
  97 #ifdef __PRE_RAM__
  98         if (ConfigPtr == NULL)
  99                 return AGESA_ERROR;
 100
 101         select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
 102
 103         Status = agesa_ReadSpd (Func, Data, ConfigPtr);
 104
 105         restore_socket();
 106 #else
 107         Status = AGESA_UNSUPPORTED;
 108 #endif
 109
 110         return Status;
 111 }
 112
 113 static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost)
 114 {
 115         InitPost->MemConfig.UmaMode = UMA_AUTO;
 116         InitPost->MemConfig.BottomIo = 0xE0;
 117         InitPost->MemConfig.UmaSize = 0xE0-0xC0;
 118         return AGESA_SUCCESS;
 119 }
 120
 121 const struct OEM_HOOK OemCustomize = {
 122         .InitPost = OemInitPost,
 123 };