src/mainboard/amd/bimini_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 //#define SYSTEM_TYPE 0 /* SERVER */
  17 #define SYSTEM_TYPE 1   /* DESKTOP */
  18 //#define SYSTEM_TYPE 2 /* MOBILE */
  19
  20 //used by incoherent_ht
  21 #define FAM10_SCAN_PCI_BUS 0
  22 #define FAM10_ALLOCATE_IO_RANGE 0
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <console/console.h>
  32 #include <timestamp.h>
  33 #include <cpu/amd/model_10xxx_rev.h>
  34 #include <northbridge/amd/amdfam10/raminit.h>
  35 #include <northbridge/amd/amdfam10/amdfam10.h>
  36 #include <lib.h>
  37 #include <cpu/x86/lapic.h>
  38 #include "northbridge/amd/amdfam10/reset_test.c"
  39 #include <commonlib/loglevel.h>
  40 #include <cpu/x86/bist.h>
  41 #include <cpu/amd/mtrr.h>
  42 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  43 #include "southbridge/amd/rs780/early_setup.c"
  44 #include "southbridge/amd/sb800/early_setup.c"
  45 #include "northbridge/amd/amdfam10/debug.c"
  46 #include <spd.h>
  47
  48 static void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50 }
  51
  52 static int spd_read_byte(u32 device, u32 address)
  53 {
  54         return smbus_read_byte(device, address);
  55 }
  56
  57 #include <northbridge/amd/amdfam10/amdfam10.h>
  58 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  59 #include "northbridge/amd/amdfam10/pci.c"
  60 #include "resourcemap.c"
  61 #include "cpu/amd/quadcore/quadcore.c"
  62 #include <cpu/amd/microcode.h>
  63
  64 #include "cpu/amd/model_10xxx/init_cpus.c"
  65 #include "northbridge/amd/amdfam10/early_ht.c"
  66
  67 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  68 {
  69         struct sys_info *sysinfo = &sysinfo_car;
  70         static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
  71         u32 bsp_apicid = 0, val;
  72         msr_t msr;
  73
  74         timestamp_init(timestamp_get());
  75         timestamp_add_now(TS_START_ROMSTAGE);
  76
  77         if (!cpu_init_detectedx && boot_cpu()) {
  78                 /* Nothing special needs to be done to find bus 0 */
  79                 /* Allow the HT devices to be found */
  80                 /* mov bsp to bus 0xff when > 8 nodes */
  81                 set_bsp_node_CHtExtNodeCfgEn();
  82                 enumerate_ht_chain();
  83
  84                 /* enable port80 decoding and southbridge poweron init */
  85                 sb800_lpc_port80();
  86                 inb(0x80);      /* Wait sometime before post to port80, otherwise reset was needed. */
  87         }
  88
  89         post_code(0x30);
  90
  91         if (bist == 0) {
  92                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
  93                 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
  94         }
  95
  96         post_code(0x32);
  97
  98         enable_rs780_dev8();
  99         sb800_lpc_init();
 100
 101         console_init();
 102
 103 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 104
 105         /* Halt if there was a built in self test failure */
 106         report_bist_failure(bist);
 107
 108         // Load MPB
 109         val = cpuid_eax(1);
 110         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 111         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 112         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 113         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 114
 115         /* Setup sysinfo defaults */
 116         set_sysinfo_in_ram(0);
 117
 118         update_microcode(val);
 119
 120         post_code(0x33);
 121
 122         cpuSetAMDMSR();
 123         post_code(0x34);
 124
 125         amd_ht_init(sysinfo);
 126         post_code(0x35);
 127
 128         /* Setup nodes PCI space and start core 0 AP init. */
 129         finalize_node_setup(sysinfo);
 130
 131         /* Setup any mainboard PCI settings etc. */
 132         setup_mb_resource_map();
 133         post_code(0x36);
 134
 135         /* wait for all the APs core0 started by finalize_node_setup. */
 136         /* FIXME: A bunch of cores are going to start output to serial at once.
 137            It would be nice to fixup prink spinlocks for ROM XIP mode.
 138            I think it could be done by putting the spinlock flag in the cache
 139            of the BSP located right after sysinfo.
 140          */
 141         wait_all_core0_started();
 142
 143 #if CONFIG_LOGICAL_CPUS
 144         /* Core0 on each node is configured. Now setup any additional cores. */
 145         printk(BIOS_DEBUG, "start_other_cores()\n");
 146         start_other_cores();
 147         post_code(0x37);
 148         wait_all_other_cores_started(bsp_apicid);
 149 #endif
 150
 151         post_code(0x38);
 152
 153         /* run _early_setup before soft-reset. */
 154         rs780_early_setup();
 155         sb800_early_setup();
 156
 157 #if CONFIG_SET_FIDVID
 158         msr = rdmsr(0xc0010071);
 159         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 160
 161         /* FIXME: The sb fid change may survive the warm reset and only
 162            need to be done once.*/
 163         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 164
 165         post_code(0x39);
 166
 167         if (!warm_reset_detect(0)) {                    // BSP is node 0
 168                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 169         } else {
 170                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 171         }
 172
 173         post_code(0x3A);
 174
 175         /* show final fid and vid */
 176         msr=rdmsr(0xc0010071);
 177         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 178 #endif
 179
 180         rs780_htinit();
 181
 182         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 183         if (!warm_reset_detect(0)) {
 184                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 185                 soft_reset();
 186                 die("After soft_reset_x - shouldn't see this message!!!\n");
 187         }
 188
 189         post_code(0x3B);
 190
 191         /* It's the time to set ctrl in sysinfo now; */
 192         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 193         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 194
 195         post_code(0x40);
 196
 197 //      die("Die Before MCT init.");
 198
 199         timestamp_add_now(TS_BEFORE_INITRAM);
 200         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 201         raminit_amdmct(sysinfo);
 202         timestamp_add_now(TS_AFTER_INITRAM);
 203
 204         cbmem_initialize_empty();
 205         post_code(0x41);
 206
 207         amdmct_cbmem_store_info(sysinfo);
 208
 209 /*
 210         dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
 211         dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
 212         dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
 213         dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 214 */
 215
 216 //      ram_check(0x00200000, 0x00200000 + (640 * 1024));
 217 //      ram_check(0x40200000, 0x40200000 + (640 * 1024));
 218
 219 //      die("After MCT init before CAR disabled.");
 220
 221         rs780_before_pci_init();
 222         sb800_before_pci_init();
 223
 224         post_code(0x42);
 225         post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
 226         post_code(0x43);        // Should never see this post code.
 227 }
 228
 229 /**
 230  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 231  * Description:
 232  *      This routine is called every time a non-coherent chain is processed.
 233  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 234  *      swap list. The first part of the list controls the BUID assignment and the
 235  *      second part of the list provides the device to device linking.  Device orientation
 236  *      can be detected automatically, or explicitly.  See documentation for more details.
 237  *
 238  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 239  *      based on each device's unit count.
 240  *
 241  * Parameters:
 242  *      @param[in]  node   = The node on which this chain is located
 243  *      @param[in]  link   = The link on the host for this chain
 244  *      @param[out] List   = supply a pointer to a list
 245  */
 246 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 247 {
 248         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 249         /* If the BUID was adjusted in early_ht we need to do the manual override */
 250                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 251                         *List = swaplist;
 252                         return 1;
 253                 }
 254
 255         return 0;
 256 }