| blob | 63a34fd33a7ce665d9aa5c7d81d658572027179e |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 DefinitionBlock (
18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
21 "ADVANSUS", /* OEMID */
22 "COREBOOT", /* TABLE ID */
23 0x00010001 /* OEM Revision */
24 )
25 { /* Start of ASL file */
26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28 /* Data to be patched by the BIOS during POST */
29 /* FIXME the patching is not done yet! */
30 /* Memory related values */
31 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
32 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
33 Name(PBLN, 0x0) /* Length of BIOS area */
35 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
36 Name(HPBA, 0xFED00000) /* Base address of HPET table */
38 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
40 /* USB overcurrent mapping pins. */
41 Name(UOM0, 0)
42 Name(UOM1, 2)
43 Name(UOM2, 0)
44 Name(UOM3, 7)
45 Name(UOM4, 2)
46 Name(UOM5, 2)
47 Name(UOM6, 6)
48 Name(UOM7, 2)
49 Name(UOM8, 6)
50 Name(UOM9, 6)
52 /* Some global data */
53 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
54 Name(OSV, Ones) /* Assume nothing */
55 Name(PMOD, One) /* Assume APIC */
57 /*
58 * Processor Object
59 *
60 */
61 Scope (\_PR) { /* define processor scope */
62 Processor(
63 CPU0, /* name space name */
64 0, /* Unique number for this processor */
65 0x808, /* PBLK system I/O address !hardcoded! */
66 0x06 /* PBLKLEN for boot processor */
67 ) {
68 #include "acpi/cpstate.asl"
69 }
71 Processor(
72 CPU1, /* name space name */
73 1, /* Unique number for this processor */
74 0x0000, /* PBLK system I/O address !hardcoded! */
75 0x00 /* PBLKLEN for boot processor */
76 ) {
77 #include "acpi/cpstate.asl"
78 }
80 Processor(
81 CPU2, /* name space name */
82 2, /* Unique number for this processor */
83 0x0000, /* PBLK system I/O address !hardcoded! */
84 0x00 /* PBLKLEN for boot processor */
85 ) {
86 #include "acpi/cpstate.asl"
87 }
89 Processor(
90 CPU3, /* name space name */
91 3, /* Unique number for this processor */
92 0x0000, /* PBLK system I/O address !hardcoded! */
93 0x00 /* PBLKLEN for boot processor */
94 ) {
95 #include "acpi/cpstate.asl"
96 }
97 } /* End _PR scope */
99 /* PIC IRQ mapping registers, C00h-C01h. */
100 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
101 Field(PRQM, ByteAcc, NoLock, Preserve) {
102 PRQI, 0x00000008,
103 PRQD, 0x00000008, /* Offset: 1h */
104 }
105 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
106 PIRA, 0x00000008, /* Index 0 */
107 PIRB, 0x00000008, /* Index 1 */
108 PIRC, 0x00000008, /* Index 2 */
109 PIRD, 0x00000008, /* Index 3 */
110 PIRE, 0x00000008, /* Index 4 */
111 PIRF, 0x00000008, /* Index 5 */
112 PIRG, 0x00000008, /* Index 6 */
113 PIRH, 0x00000008, /* Index 7 */
114 }
116 /* PCI Error control register */
117 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
118 Field(PERC, ByteAcc, NoLock, Preserve) {
119 SENS, 0x00000001,
120 PENS, 0x00000001,
121 SENE, 0x00000001,
122 PENE, 0x00000001,
123 }
125 /* Client Management index/data registers */
126 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
127 Field(CMT, ByteAcc, NoLock, Preserve) {
128 CMTI, 8,
129 /* Client Management Data register */
130 G64E, 1,
131 G64O, 1,
132 G32O, 2,
133 , 2,
134 GPSL, 2,
135 }
137 /* GPM Port register */
138 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
139 Field(GPT, ByteAcc, NoLock, Preserve) {
140 GPB0,1,
141 GPB1,1,
142 GPB2,1,
143 GPB3,1,
144 GPB4,1,
145 GPB5,1,
146 GPB6,1,
147 GPB7,1,
148 }
150 /* Flash ROM program enable register */
151 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
152 Field(FRE, ByteAcc, NoLock, Preserve) {
153 , 0x00000006,
154 FLRE, 0x00000001,
155 }
157 /* PM2 index/data registers */
158 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
159 Field(PM2R, ByteAcc, NoLock, Preserve) {
160 PM2I, 0x00000008,
161 PM2D, 0x00000008,
162 }
164 /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
165 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
166 Field(PIOR, ByteAcc, NoLock, Preserve) {
167 PIOI, 0x00000008,
168 PIOD, 0x00000008,
169 }
170 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
171 Offset(0x00), /* MiscControl */
172 , 1,
173 T1EE, 1,
174 T2EE, 1,
175 Offset(0x01), /* MiscStatus */
176 , 1,
177 T1E, 1,
178 T2E, 1,
179 Offset(0x04), /* SmiWakeUpEventEnable3 */
180 , 7,
181 SSEN, 1,
182 Offset(0x07), /* SmiWakeUpEventStatus3 */
183 , 7,
184 CSSM, 1,
185 Offset(0x10), /* AcpiEnable */
186 , 6,
187 PWDE, 1,
188 Offset(0x1C), /* ProgramIoEnable */
189 , 3,
190 MKME, 1,
191 IO3E, 1,
192 IO2E, 1,
193 IO1E, 1,
194 IO0E, 1,
195 Offset(0x1D), /* IOMonitorStatus */
196 , 3,
197 MKMS, 1,
198 IO3S, 1,
199 IO2S, 1,
200 IO1S, 1,
201 IO0S,1,
202 Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
203 APEB, 16,
204 Offset(0x36), /* GEvtLevelConfig */
205 , 6,
206 ELC6, 1,
207 ELC7, 1,
208 Offset(0x37), /* GPMLevelConfig0 */
209 , 3,
210 PLC0, 1,
211 PLC1, 1,
212 PLC2, 1,
213 PLC3, 1,
214 PLC8, 1,
215 Offset(0x38), /* GPMLevelConfig1 */
216 , 1,
217 PLC4, 1,
218 PLC5, 1,
219 , 1,
220 PLC6, 1,
221 PLC7, 1,
222 Offset(0x3B), /* PMEStatus1 */
223 GP0S, 1,
224 GM4S, 1,
225 GM5S, 1,
226 APS, 1,
227 GM6S, 1,
228 GM7S, 1,
229 GP2S, 1,
230 STSS, 1,
231 Offset(0x55), /* SoftPciRst */
232 SPRE, 1,
233 , 1,
234 , 1,
235 PNAT, 1,
236 PWMK, 1,
237 PWNS, 1,
239 /* Offset(0x61), */ /* Options_1 */
240 /* ,7, */
241 /* R617,1, */
243 Offset(0x65), /* UsbPMControl */
244 , 4,
245 URRE, 1,
246 Offset(0x68), /* MiscEnable68 */
247 , 3,
248 TMTE, 1,
249 , 1,
250 Offset(0x92), /* GEVENTIN */
251 , 7,
252 E7IS, 1,
253 Offset(0x96), /* GPM98IN */
254 G8IS, 1,
255 G9IS, 1,
256 Offset(0x9A), /* EnhanceControl */
257 ,7,
258 HPDE, 1,
259 Offset(0xA8), /* PIO7654Enable */
260 IO4E, 1,
261 IO5E, 1,
262 IO6E, 1,
263 IO7E, 1,
264 Offset(0xA9), /* PIO7654Status */
265 IO4S, 1,
266 IO5S, 1,
267 IO6S, 1,
268 IO7S, 1,
269 }
271 /* PM1 Event Block
272 * First word is PM1_Status, Second word is PM1_Enable
273 */
274 OperationRegion(P1EB, SystemIO, APEB, 0x04)
275 Field(P1EB, ByteAcc, NoLock, Preserve) {
276 TMST, 1,
277 , 3,
278 BMST, 1,
279 GBST, 1,
280 Offset(0x01),
281 PBST, 1,
282 , 1,
283 RTST, 1,
284 , 3,
285 PWST, 1,
286 SPWS, 1,
287 Offset(0x02),
288 TMEN, 1,
289 , 4,
290 GBEN, 1,
291 Offset(0x03),
292 PBEN, 1,
293 , 1,
294 RTEN, 1,
295 , 3,
296 PWDA, 1,
297 }
299 Scope(\_SB) {
300 /* PCIe Configuration Space for 16 busses */
301 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
302 Field(PCFG, ByteAcc, NoLock, Preserve) {
303 /* Byte offsets are computed using the following technique:
304 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
305 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
306 */
307 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
308 STB5, 32,
309 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
310 PT0D, 1,
311 PT1D, 1,
312 PT2D, 1,
313 PT3D, 1,
314 PT4D, 1,
315 PT5D, 1,
316 PT6D, 1,
317 PT7D, 1,
318 PT8D, 1,
319 PT9D, 1,
320 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
321 SBIE, 1,
322 SBME, 1,
323 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
324 SBRI, 8,
325 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
326 SBB1, 32,
327 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
328 ,14,
329 P92E, 1, /* Port92 decode enable */
330 }
332 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
333 Field(SB5, AnyAcc, NoLock, Preserve){
334 /* Port 0 */
335 Offset(0x120), /* Port 0 Task file status */
336 P0ER, 1,
337 , 2,
338 P0DQ, 1,
339 , 3,
340 P0BY, 1,
341 Offset(0x128), /* Port 0 Serial ATA status */
342 P0DD, 4,
343 , 4,
344 P0IS, 4,
345 Offset(0x12C), /* Port 0 Serial ATA control */
346 P0DI, 4,
347 Offset(0x130), /* Port 0 Serial ATA error */
348 , 16,
349 P0PR, 1,
351 /* Port 1 */
352 offset(0x1A0), /* Port 1 Task file status */
353 P1ER, 1,
354 , 2,
355 P1DQ, 1,
356 , 3,
357 P1BY, 1,
358 Offset(0x1A8), /* Port 1 Serial ATA status */
359 P1DD, 4,
360 , 4,
361 P1IS, 4,
362 Offset(0x1AC), /* Port 1 Serial ATA control */
363 P1DI, 4,
364 Offset(0x1B0), /* Port 1 Serial ATA error */
365 , 16,
366 P1PR, 1,
368 /* Port 2 */
369 Offset(0x220), /* Port 2 Task file status */
370 P2ER, 1,
371 , 2,
372 P2DQ, 1,
373 , 3,
374 P2BY, 1,
375 Offset(0x228), /* Port 2 Serial ATA status */
376 P2DD, 4,
377 , 4,
378 P2IS, 4,
379 Offset(0x22C), /* Port 2 Serial ATA control */
380 P2DI, 4,
381 Offset(0x230), /* Port 2 Serial ATA error */
382 , 16,
383 P2PR, 1,
385 /* Port 3 */
386 Offset(0x2A0), /* Port 3 Task file status */
387 P3ER, 1,
388 , 2,
389 P3DQ, 1,
390 , 3,
391 P3BY, 1,
392 Offset(0x2A8), /* Port 3 Serial ATA status */
393 P3DD, 4,
394 , 4,
395 P3IS, 4,
396 Offset(0x2AC), /* Port 3 Serial ATA control */
397 P3DI, 4,
398 Offset(0x2B0), /* Port 3 Serial ATA error */
399 , 16,
400 P3PR, 1,
401 }
402 }
405 #include "acpi/routing.asl"
407 Scope(\_SB) {
409 Method(OSFL, 0){
411 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
413 if(CondRefOf(\_OSI,Local1))
414 {
415 Store(1, OSVR) /* Assume some form of XP */
416 if (\_OSI("Windows 2006")) /* Vista */
417 {
418 Store(2, OSVR)
419 }
420 } else {
421 If(WCMP(\_OS,"Linux")) {
422 Store(3, OSVR) /* Linux */
423 } Else {
424 Store(4, OSVR) /* Gotta be WinCE */
425 }
426 }
427 Return(OSVR)
428 }
430 Method(_PIC, 0x01, NotSerialized)
431 {
432 If (Arg0)
433 {
434 \_SB.CIRQ()
435 }
436 Store(Arg0, PMOD)
437 }
438 Method(CIRQ, 0x00, NotSerialized){
439 Store(0, PIRA)
440 Store(0, PIRB)
441 Store(0, PIRC)
442 Store(0, PIRD)
443 Store(0, PIRE)
444 Store(0, PIRF)
445 Store(0, PIRG)
446 Store(0, PIRH)
447 }
449 Name(IRQB, ResourceTemplate(){
450 IRQ(Level,ActiveLow,Shared){15}
451 })
453 Name(IRQP, ResourceTemplate(){
454 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
455 })
457 Name(PITF, ResourceTemplate(){
458 IRQ(Level,ActiveLow,Exclusive){9}
459 })
461 Device(INTA) {
462 Name(_HID, EISAID("PNP0C0F"))
463 Name(_UID, 1)
465 Method(_STA, 0) {
466 if (PIRA) {
467 Return(0x0B) /* sata is invisible */
468 } else {
469 Return(0x09) /* sata is disabled */
470 }
471 } /* End Method(_SB.INTA._STA) */
473 Method(_DIS ,0) {
474 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
475 Store(0, PIRA)
476 } /* End Method(_SB.INTA._DIS) */
478 Method(_PRS ,0) {
479 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
480 Return(IRQP)
481 } /* Method(_SB.INTA._PRS) */
483 Method(_CRS ,0) {
484 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
485 CreateWordField(IRQB, 0x1, IRQN)
486 ShiftLeft(1, PIRA, IRQN)
487 Return(IRQB)
488 } /* Method(_SB.INTA._CRS) */
490 Method(_SRS, 1) {
491 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
492 CreateWordField(ARG0, 1, IRQM)
494 /* Use lowest available IRQ */
495 FindSetRightBit(IRQM, Local0)
496 if (Local0) {
497 Decrement(Local0)
498 }
499 Store(Local0, PIRA)
500 } /* End Method(_SB.INTA._SRS) */
501 } /* End Device(INTA) */
503 Device(INTB) {
504 Name(_HID, EISAID("PNP0C0F"))
505 Name(_UID, 2)
507 Method(_STA, 0) {
508 if (PIRB) {
509 Return(0x0B) /* sata is invisible */
510 } else {
511 Return(0x09) /* sata is disabled */
512 }
513 } /* End Method(_SB.INTB._STA) */
515 Method(_DIS ,0) {
516 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
517 Store(0, PIRB)
518 } /* End Method(_SB.INTB._DIS) */
520 Method(_PRS ,0) {
521 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
522 Return(IRQP)
523 } /* Method(_SB.INTB._PRS) */
525 Method(_CRS ,0) {
526 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
527 CreateWordField(IRQB, 0x1, IRQN)
528 ShiftLeft(1, PIRB, IRQN)
529 Return(IRQB)
530 } /* Method(_SB.INTB._CRS) */
532 Method(_SRS, 1) {
533 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
534 CreateWordField(ARG0, 1, IRQM)
536 /* Use lowest available IRQ */
537 FindSetRightBit(IRQM, Local0)
538 if (Local0) {
539 Decrement(Local0)
540 }
541 Store(Local0, PIRB)
542 } /* End Method(_SB.INTB._SRS) */
543 } /* End Device(INTB) */
545 Device(INTC) {
546 Name(_HID, EISAID("PNP0C0F"))
547 Name(_UID, 3)
549 Method(_STA, 0) {
550 if (PIRC) {
551 Return(0x0B) /* sata is invisible */
552 } else {
553 Return(0x09) /* sata is disabled */
554 }
555 } /* End Method(_SB.INTC._STA) */
557 Method(_DIS ,0) {
558 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
559 Store(0, PIRC)
560 } /* End Method(_SB.INTC._DIS) */
562 Method(_PRS ,0) {
563 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
564 Return(IRQP)
565 } /* Method(_SB.INTC._PRS) */
567 Method(_CRS ,0) {
568 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
569 CreateWordField(IRQB, 0x1, IRQN)
570 ShiftLeft(1, PIRC, IRQN)
571 Return(IRQB)
572 } /* Method(_SB.INTC._CRS) */
574 Method(_SRS, 1) {
575 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
576 CreateWordField(ARG0, 1, IRQM)
578 /* Use lowest available IRQ */
579 FindSetRightBit(IRQM, Local0)
580 if (Local0) {
581 Decrement(Local0)
582 }
583 Store(Local0, PIRC)
584 } /* End Method(_SB.INTC._SRS) */
585 } /* End Device(INTC) */
587 Device(INTD) {
588 Name(_HID, EISAID("PNP0C0F"))
589 Name(_UID, 4)
591 Method(_STA, 0) {
592 if (PIRD) {
593 Return(0x0B) /* sata is invisible */
594 } else {
595 Return(0x09) /* sata is disabled */
596 }
597 } /* End Method(_SB.INTD._STA) */
599 Method(_DIS ,0) {
600 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
601 Store(0, PIRD)
602 } /* End Method(_SB.INTD._DIS) */
604 Method(_PRS ,0) {
605 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
606 Return(IRQP)
607 } /* Method(_SB.INTD._PRS) */
609 Method(_CRS ,0) {
610 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
611 CreateWordField(IRQB, 0x1, IRQN)
612 ShiftLeft(1, PIRD, IRQN)
613 Return(IRQB)
614 } /* Method(_SB.INTD._CRS) */
616 Method(_SRS, 1) {
617 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
618 CreateWordField(ARG0, 1, IRQM)
620 /* Use lowest available IRQ */
621 FindSetRightBit(IRQM, Local0)
622 if (Local0) {
623 Decrement(Local0)
624 }
625 Store(Local0, PIRD)
626 } /* End Method(_SB.INTD._SRS) */
627 } /* End Device(INTD) */
629 Device(INTE) {
630 Name(_HID, EISAID("PNP0C0F"))
631 Name(_UID, 5)
633 Method(_STA, 0) {
634 if (PIRE) {
635 Return(0x0B) /* sata is invisible */
636 } else {
637 Return(0x09) /* sata is disabled */
638 }
639 } /* End Method(_SB.INTE._STA) */
641 Method(_DIS ,0) {
642 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
643 Store(0, PIRE)
644 } /* End Method(_SB.INTE._DIS) */
646 Method(_PRS ,0) {
647 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
648 Return(IRQP)
649 } /* Method(_SB.INTE._PRS) */
651 Method(_CRS ,0) {
652 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
653 CreateWordField(IRQB, 0x1, IRQN)
654 ShiftLeft(1, PIRE, IRQN)
655 Return(IRQB)
656 } /* Method(_SB.INTE._CRS) */
658 Method(_SRS, 1) {
659 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
660 CreateWordField(ARG0, 1, IRQM)
662 /* Use lowest available IRQ */
663 FindSetRightBit(IRQM, Local0)
664 if (Local0) {
665 Decrement(Local0)
666 }
667 Store(Local0, PIRE)
668 } /* End Method(_SB.INTE._SRS) */
669 } /* End Device(INTE) */
671 Device(INTF) {
672 Name(_HID, EISAID("PNP0C0F"))
673 Name(_UID, 6)
675 Method(_STA, 0) {
676 if (PIRF) {
677 Return(0x0B) /* sata is invisible */
678 } else {
679 Return(0x09) /* sata is disabled */
680 }
681 } /* End Method(_SB.INTF._STA) */
683 Method(_DIS ,0) {
684 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
685 Store(0, PIRF)
686 } /* End Method(_SB.INTF._DIS) */
688 Method(_PRS ,0) {
689 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
690 Return(PITF)
691 } /* Method(_SB.INTF._PRS) */
693 Method(_CRS ,0) {
694 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
695 CreateWordField(IRQB, 0x1, IRQN)
696 ShiftLeft(1, PIRF, IRQN)
697 Return(IRQB)
698 } /* Method(_SB.INTF._CRS) */
700 Method(_SRS, 1) {
701 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
702 CreateWordField(ARG0, 1, IRQM)
704 /* Use lowest available IRQ */
705 FindSetRightBit(IRQM, Local0)
706 if (Local0) {
707 Decrement(Local0)
708 }
709 Store(Local0, PIRF)
710 } /* End Method(_SB.INTF._SRS) */
711 } /* End Device(INTF) */
713 Device(INTG) {
714 Name(_HID, EISAID("PNP0C0F"))
715 Name(_UID, 7)
717 Method(_STA, 0) {
718 if (PIRG) {
719 Return(0x0B) /* sata is invisible */
720 } else {
721 Return(0x09) /* sata is disabled */
722 }
723 } /* End Method(_SB.INTG._STA) */
725 Method(_DIS ,0) {
726 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
727 Store(0, PIRG)
728 } /* End Method(_SB.INTG._DIS) */
730 Method(_PRS ,0) {
731 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
732 Return(IRQP)
733 } /* Method(_SB.INTG._CRS) */
735 Method(_CRS ,0) {
736 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
737 CreateWordField(IRQB, 0x1, IRQN)
738 ShiftLeft(1, PIRG, IRQN)
739 Return(IRQB)
740 } /* Method(_SB.INTG._CRS) */
742 Method(_SRS, 1) {
743 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
744 CreateWordField(ARG0, 1, IRQM)
746 /* Use lowest available IRQ */
747 FindSetRightBit(IRQM, Local0)
748 if (Local0) {
749 Decrement(Local0)
750 }
751 Store(Local0, PIRG)
752 } /* End Method(_SB.INTG._SRS) */
753 } /* End Device(INTG) */
755 Device(INTH) {
756 Name(_HID, EISAID("PNP0C0F"))
757 Name(_UID, 8)
759 Method(_STA, 0) {
760 if (PIRH) {
761 Return(0x0B) /* sata is invisible */
762 } else {
763 Return(0x09) /* sata is disabled */
764 }
765 } /* End Method(_SB.INTH._STA) */
767 Method(_DIS ,0) {
768 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
769 Store(0, PIRH)
770 } /* End Method(_SB.INTH._DIS) */
772 Method(_PRS ,0) {
773 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
774 Return(IRQP)
775 } /* Method(_SB.INTH._CRS) */
777 Method(_CRS ,0) {
778 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
779 CreateWordField(IRQB, 0x1, IRQN)
780 ShiftLeft(1, PIRH, IRQN)
781 Return(IRQB)
782 } /* Method(_SB.INTH._CRS) */
784 Method(_SRS, 1) {
785 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
786 CreateWordField(ARG0, 1, IRQM)
788 /* Use lowest available IRQ */
789 FindSetRightBit(IRQM, Local0)
790 if (Local0) {
791 Decrement(Local0)
792 }
793 Store(Local0, PIRH)
794 } /* End Method(_SB.INTH._SRS) */
795 } /* End Device(INTH) */
797 } /* End Scope(_SB) */
800 /* Supported sleep states: */
801 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
803 If (LAnd(SSFG, 0x01)) {
804 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
805 }
806 If (LAnd(SSFG, 0x02)) {
807 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
808 }
809 If (LAnd(SSFG, 0x04)) {
810 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
811 }
812 If (LAnd(SSFG, 0x08)) {
813 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
814 }
816 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
818 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
819 Name(CSMS, 0) /* Current System State */
821 /* Wake status package */
822 Name(WKST,Package(){Zero, Zero})
824 /*
825 * \_PTS - Prepare to Sleep method
826 *
827 * Entry:
828 * Arg0=The value of the sleeping state S1=1, S2=2, etc
829 *
830 * Exit:
831 * -none-
832 *
833 * The _PTS control method is executed at the beginning of the sleep process
834 * for S1-S5. The sleeping value is passed to the _PTS control method. This
835 * control method may be executed a relatively long time before entering the
836 * sleep state and the OS may abort the operation without notification to
837 * the ACPI driver. This method cannot modify the configuration or power
838 * state of any device in the system.
839 */
840 Method(\_PTS, 1) {
841 /* DBGO("\\_PTS\n") */
842 /* DBGO("From S0 to S") */
843 /* DBGO(Arg0) */
844 /* DBGO("\n") */
846 /* Don't allow PCIRST# to reset USB */
847 if (LEqual(Arg0,3)){
848 Store(0,URRE)
849 }
851 /* Clear sleep SMI status flag and enable sleep SMI trap. */
852 /*Store(One, CSSM)
853 Store(One, SSEN)*/
855 /* On older chips, clear PciExpWakeDisEn */
856 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
857 * Store(0,\_SB.PWDE)
858 *}
859 */
861 /* Clear wake status structure. */
862 Store(0, Index(WKST,0))
863 Store(0, Index(WKST,1))
864 } /* End Method(\_PTS) */
866 /*
867 * The following method results in a "not a valid reserved NameSeg"
868 * warning so I have commented it out for the duration. It isn't
869 * used, so it could be removed.
870 *
871 *
872 * \_GTS OEM Going To Sleep method
873 *
874 * Entry:
875 * Arg0=The value of the sleeping state S1=1, S2=2
876 *
877 * Exit:
878 * -none-
879 *
880 * Method(\_GTS, 1) {
881 * DBGO("\\_GTS\n")
882 * DBGO("From S0 to S")
883 * DBGO(Arg0)
884 * DBGO("\n")
885 * }
886 */
888 /*
889 * \_BFS OEM Back From Sleep method
890 *
891 * Entry:
892 * Arg0=The value of the sleeping state S1=1, S2=2
893 *
894 * Exit:
895 * -none-
896 */
897 Method(\_BFS, 1) {
898 /* DBGO("\\_BFS\n") */
899 /* DBGO("From S") */
900 /* DBGO(Arg0) */
901 /* DBGO(" to S0\n") */
902 }
904 /*
905 * \_WAK System Wake method
906 *
907 * Entry:
908 * Arg0=The value of the sleeping state S1=1, S2=2
909 *
910 * Exit:
911 * Return package of 2 DWords
912 * Dword 1 - Status
913 * 0x00000000 wake succeeded
914 * 0x00000001 Wake was signaled but failed due to lack of power
915 * 0x00000002 Wake was signaled but failed due to thermal condition
916 * Dword 2 - Power Supply state
917 * if non-zero the effective S-state the power supply entered
918 */
919 Method(\_WAK, 1) {
920 /* DBGO("\\_WAK\n") */
921 /* DBGO("From S") */
922 /* DBGO(Arg0) */
923 /* DBGO(" to S0\n") */
925 /* Re-enable HPET */
926 Store(1,HPDE)
928 /* Restore PCIRST# so it resets USB */
929 if (LEqual(Arg0,3)){
930 Store(1,URRE)
931 }
933 /* Arbitrarily clear PciExpWakeStatus */
934 Store(PWST, PWST)
936 /* if(DeRefOf(Index(WKST,0))) {
937 * Store(0, Index(WKST,1))
938 * } else {
939 * Store(Arg0, Index(WKST,1))
940 * }
941 */
942 Return(WKST)
943 } /* End Method(\_WAK) */
945 Scope(\_GPE) { /* Start Scope GPE */
946 /* General event 0 */
947 /* Method(_L00) {
948 * DBGO("\\_GPE\\_L00\n")
949 * }
950 */
952 /* General event 1 */
953 /* Method(_L01) {
954 * DBGO("\\_GPE\\_L00\n")
955 * }
956 */
958 /* General event 2 */
959 /* Method(_L02) {
960 * DBGO("\\_GPE\\_L00\n")
961 * }
962 */
964 /* General event 3 */
965 Method(_L03) {
966 /* DBGO("\\_GPE\\_L00\n") */
967 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
968 }
970 /* General event 4 */
971 /* Method(_L04) {
972 * DBGO("\\_GPE\\_L00\n")
973 * }
974 */
976 /* General event 5 */
977 /* Method(_L05) {
978 * DBGO("\\_GPE\\_L00\n")
979 * }
980 */
982 /* General event 6 - Used for GPM6, moved to USB.asl */
983 /* Method(_L06) {
984 * DBGO("\\_GPE\\_L00\n")
985 * }
986 */
988 /* General event 7 - Used for GPM7, moved to USB.asl */
989 /* Method(_L07) {
990 * DBGO("\\_GPE\\_L07\n")
991 * }
992 */
994 /* Legacy PM event */
995 Method(_L08) {
996 /* DBGO("\\_GPE\\_L08\n") */
997 }
999 /* Temp warning (TWarn) event */
1000 Method(_L09) {
1001 /* DBGO("\\_GPE\\_L09\n") */
1002 /* Notify (\_TZ.TZ00, 0x80) */
1003 }
1005 /* Reserved */
1006 /* Method(_L0A) {
1007 * DBGO("\\_GPE\\_L0A\n")
1008 * }
1009 */
1011 /* USB controller PME# */
1012 Method(_L0B) {
1013 /* DBGO("\\_GPE\\_L0B\n") */
1014 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1015 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1016 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1017 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1018 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1019 Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1020 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1021 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1022 }
1024 /* AC97 controller PME# */
1025 /* Method(_L0C) {
1026 * DBGO("\\_GPE\\_L0C\n")
1027 * }
1028 */
1030 /* OtherTherm PME# */
1031 /* Method(_L0D) {
1032 * DBGO("\\_GPE\\_L0D\n")
1033 * }
1034 */
1036 /* GPM9 SCI event - Moved to USB.asl */
1037 /* Method(_L0E) {
1038 * DBGO("\\_GPE\\_L0E\n")
1039 * }
1040 */
1042 /* PCIe HotPlug event */
1043 /* Method(_L0F) {
1044 * DBGO("\\_GPE\\_L0F\n")
1045 * }
1046 */
1048 /* ExtEvent0 SCI event */
1049 Method(_L10) {
1050 /* DBGO("\\_GPE\\_L10\n") */
1051 }
1054 /* ExtEvent1 SCI event */
1055 Method(_L11) {
1056 /* DBGO("\\_GPE\\_L11\n") */
1057 }
1059 /* PCIe PME# event */
1060 /* Method(_L12) {
1061 * DBGO("\\_GPE\\_L12\n")
1062 * }
1063 */
1065 /* GPM0 SCI event - Moved to USB.asl */
1066 /* Method(_L13) {
1067 * DBGO("\\_GPE\\_L13\n")
1068 * }
1069 */
1071 /* GPM1 SCI event - Moved to USB.asl */
1072 /* Method(_L14) {
1073 * DBGO("\\_GPE\\_L14\n")
1074 * }
1075 */
1077 /* GPM2 SCI event - Moved to USB.asl */
1078 /* Method(_L15) {
1079 * DBGO("\\_GPE\\_L15\n")
1080 * }
1081 */
1083 /* GPM3 SCI event - Moved to USB.asl */
1084 /* Method(_L16) {
1085 * DBGO("\\_GPE\\_L16\n")
1086 * }
1087 */
1089 /* GPM8 SCI event - Moved to USB.asl */
1090 /* Method(_L17) {
1091 * DBGO("\\_GPE\\_L17\n")
1092 * }
1093 */
1095 /* GPIO0 or GEvent8 event */
1096 Method(_L18) {
1097 /* DBGO("\\_GPE\\_L18\n") */
1098 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1099 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1100 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1101 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1102 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1103 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1104 }
1106 /* GPM4 SCI event - Moved to USB.asl */
1107 /* Method(_L19) {
1108 * DBGO("\\_GPE\\_L19\n")
1109 * }
1110 */
1112 /* GPM5 SCI event - Moved to USB.asl */
1113 /* Method(_L1A) {
1114 * DBGO("\\_GPE\\_L1A\n")
1115 * }
1116 */
1118 /* Azalia SCI event */
1119 Method(_L1B) {
1120 /* DBGO("\\_GPE\\_L1B\n") */
1121 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1122 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1123 }
1125 /* GPM6 SCI event - Reassigned to _L06 */
1126 /* Method(_L1C) {
1127 * DBGO("\\_GPE\\_L1C\n")
1128 * }
1129 */
1131 /* GPM7 SCI event - Reassigned to _L07 */
1132 /* Method(_L1D) {
1133 * DBGO("\\_GPE\\_L1D\n")
1134 * }
1135 */
1137 /* GPIO2 or GPIO66 SCI event */
1138 /* Method(_L1E) {
1139 * DBGO("\\_GPE\\_L1E\n")
1140 * }
1141 */
1143 /* SATA SCI event - Moved to sata.asl */
1144 /* Method(_L1F) {
1145 * DBGO("\\_GPE\\_L1F\n")
1146 * }
1147 */
1149 } /* End Scope GPE */
1151 #include "acpi/usb.asl"
1153 /* South Bridge */
1154 Scope(\_SB) { /* Start \_SB scope */
1155 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1157 /* _SB.PCI0 */
1158 /* Note: Only need HID on Primary Bus */
1159 Device(PCI0) {
1160 External (TOM1)
1161 External (TOM2)
1162 Name(_HID, EISAID("PNP0A03"))
1163 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1164 Method(_BBN, 0) { /* Bus number = 0 */
1165 Return(0)
1166 }
1167 Method(_STA, 0) {
1168 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1169 Return(0x0B) /* Status is visible */
1170 }
1172 Method(_PRT,0) {
1173 If(PMOD){ Return(APR0) } /* APIC mode */
1174 Return (PR0) /* PIC Mode */
1175 } /* end _PRT */
1177 /* Describe the Northbridge devices */
1178 Device(AMRT) {
1179 Name(_ADR, 0x00000000)
1180 } /* end AMRT */
1182 /* The internal GFX bridge */
1183 Device(AGPB) {
1184 Name(_ADR, 0x00010000)
1185 Name(_PRW, Package() {0x18, 4})
1186 Method(_PRT,0) {
1187 Return (APR1)
1188 }
1189 } /* end AGPB */
1191 /* The external GFX bridge */
1192 Device(PBR2) {
1193 Name(_ADR, 0x00020000)
1194 Name(_PRW, Package() {0x18, 4})
1195 Method(_PRT,0) {
1196 If(PMOD){ Return(APS2) } /* APIC mode */
1197 Return (PS2) /* PIC Mode */
1198 } /* end _PRT */
1199 } /* end PBR2 */
1201 /* Dev3 is also an external GFX bridge, not used in Herring */
1203 Device(PBR4) {
1204 Name(_ADR, 0x00040000)
1205 Name(_PRW, Package() {0x18, 4})
1206 Method(_PRT,0) {
1207 If(PMOD){ Return(APS4) } /* APIC mode */
1208 Return (PS4) /* PIC Mode */
1209 } /* end _PRT */
1210 } /* end PBR4 */
1212 Device(PBR5) {
1213 Name(_ADR, 0x00050000)
1214 Name(_PRW, Package() {0x18, 4})
1215 Method(_PRT,0) {
1216 If(PMOD){ Return(APS5) } /* APIC mode */
1217 Return (PS5) /* PIC Mode */
1218 } /* end _PRT */
1219 } /* end PBR5 */
1221 Device(PBR6) {
1222 Name(_ADR, 0x00060000)
1223 Name(_PRW, Package() {0x18, 4})
1224 Method(_PRT,0) {
1225 If(PMOD){ Return(APS6) } /* APIC mode */
1226 Return (PS6) /* PIC Mode */
1227 } /* end _PRT */
1228 } /* end PBR6 */
1230 /* The onboard EtherNet chip */
1231 Device(PBR7) {
1232 Name(_ADR, 0x00070000)
1233 Name(_PRW, Package() {0x18, 4})
1234 Method(_PRT,0) {
1235 If(PMOD){ Return(APS7) } /* APIC mode */
1236 Return (PS7) /* PIC Mode */
1237 } /* end _PRT */
1238 } /* end PBR7 */
1240 /* GPP */
1241 Device(PBR9) {
1242 Name(_ADR, 0x00090000)
1243 Name(_PRW, Package() {0x18, 4})
1244 Method(_PRT,0) {
1245 If(PMOD){ Return(APS9) } /* APIC mode */
1246 Return (PS9) /* PIC Mode */
1247 } /* end _PRT */
1248 } /* end PBR9 */
1250 Device(PBRa) {
1251 Name(_ADR, 0x000A0000)
1252 Name(_PRW, Package() {0x18, 4})
1253 Method(_PRT,0) {
1254 If(PMOD){ Return(APSa) } /* APIC mode */
1255 Return (PSa) /* PIC Mode */
1256 } /* end _PRT */
1257 } /* end PBRa */
1259 Device(PE20) {
1260 Name(_ADR, 0x00150000)
1261 Name(_PRW, Package() {0x18, 4})
1262 Method(_PRT,0) {
1263 If(PMOD){ Return(APE0) } /* APIC mode */
1264 Return (PE0) /* PIC Mode */
1265 } /* end _PRT */
1266 } /* end PE20 */
1267 Device(PE21) {
1268 Name(_ADR, 0x00150001)
1269 Name(_PRW, Package() {0x18, 4})
1270 Method(_PRT,0) {
1271 If(PMOD){ Return(APE1) } /* APIC mode */
1272 Return (PE1) /* PIC Mode */
1273 } /* end _PRT */
1274 } /* end PE21 */
1275 Device(PE22) {
1276 Name(_ADR, 0x00150002)
1277 Name(_PRW, Package() {0x18, 4})
1278 Method(_PRT,0) {
1279 If(PMOD){ Return(APE2) } /* APIC mode */
1280 Return (APE2) /* PIC Mode */
1281 } /* end _PRT */
1282 } /* end PE22 */
1283 Device(PE23) {
1284 Name(_ADR, 0x00150003)
1285 Name(_PRW, Package() {0x18, 4})
1286 Method(_PRT,0) {
1287 If(PMOD){ Return(APE3) } /* APIC mode */
1288 Return (PE3) /* PIC Mode */
1289 } /* end _PRT */
1290 } /* end PE23 */
1292 /* PCI slot 1, 2, 3 */
1293 Device(PIBR) {
1294 Name(_ADR, 0x00140004)
1295 Name(_PRW, Package() {0x18, 4})
1297 Method(_PRT, 0) {
1298 Return (PCIB)
1299 }
1300 }
1302 /* Describe the Southbridge devices */
1303 Device(STCR) {
1304 Name(_ADR, 0x00110000)
1305 #include "acpi/sata.asl"
1306 } /* end STCR */
1308 Device(UOH1) {
1309 Name(_ADR, 0x00120000)
1310 Name(_PRW, Package() {0x0B, 3})
1311 } /* end UOH1 */
1313 Device(UOH2) {
1314 Name(_ADR, 0x00120002)
1315 Name(_PRW, Package() {0x0B, 3})
1316 } /* end UOH2 */
1318 Device(UOH3) {
1319 Name(_ADR, 0x00130000)
1320 Name(_PRW, Package() {0x0B, 3})
1321 } /* end UOH3 */
1323 Device(UOH4) {
1324 Name(_ADR, 0x00130002)
1325 Name(_PRW, Package() {0x0B, 3})
1326 } /* end UOH4 */
1328 Device(UOH5) {
1329 Name(_ADR, 0x00160000)
1330 Name(_PRW, Package() {0x0B, 3})
1331 } /* end UOH5 */
1333 Device(UOH6) {
1334 Name(_ADR, 0x00160002)
1335 Name(_PRW, Package() {0x0B, 3})
1336 } /* end UOH5 */
1338 Device(UEH1) {
1339 Name(_ADR, 0x00140005)
1340 Name(_PRW, Package() {0x0B, 3})
1341 } /* end UEH1 */
1343 Device(SBUS) {
1344 Name(_ADR, 0x00140000)
1345 } /* end SBUS */
1347 Device(AZHD) {
1348 Name(_ADR, 0x00140002)
1349 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1350 Field(AZPD, AnyAcc, NoLock, Preserve) {
1351 offset (0x42),
1352 NSDI, 1,
1353 NSDO, 1,
1354 NSEN, 1,
1355 offset (0x44),
1356 IPCR, 4,
1357 offset (0x54),
1358 PWST, 2,
1359 , 6,
1360 PMEB, 1,
1361 , 6,
1362 PMST, 1,
1363 offset (0x62),
1364 MMCR, 1,
1365 offset (0x64),
1366 MMLA, 32,
1367 offset (0x68),
1368 MMHA, 32,
1369 offset (0x6C),
1370 MMDT, 16,
1371 }
1373 Method(_INI) {
1374 If(LEqual(OSVR,3)){ /* If we are running Linux */
1375 Store(zero, NSEN)
1376 Store(one, NSDO)
1377 Store(one, NSDI)
1378 }
1379 }
1380 } /* end AZHD */
1382 Device(LIBR) {
1383 Name(_ADR, 0x00140003)
1384 /* Method(_INI) {
1385 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1386 } */ /* End Method(_SB.SBRDG._INI) */
1388 /* Real Time Clock Device */
1389 Device(RTC0) {
1390 Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
1391 Name(_CRS, ResourceTemplate() {
1392 IRQNoFlags(){8}
1393 IO(Decode16,0x0070, 0x0070, 0, 2)
1394 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1395 })
1396 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1398 Device(TMR) { /* Timer */
1399 Name(_HID,EISAID("PNP0100")) /* System Timer */
1400 Name(_CRS, ResourceTemplate() {
1401 IRQNoFlags(){0}
1402 IO(Decode16, 0x0040, 0x0040, 0, 4)
1403 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1404 })
1405 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1407 Device(SPKR) { /* Speaker */
1408 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1409 Name(_CRS, ResourceTemplate() {
1410 IO(Decode16, 0x0061, 0x0061, 0, 1)
1411 })
1412 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1414 Device(PIC) {
1415 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1416 Name(_CRS, ResourceTemplate() {
1417 IRQNoFlags(){2}
1418 IO(Decode16,0x0020, 0x0020, 0, 2)
1419 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1420 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1421 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1422 })
1423 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1425 Device(MAD) { /* 8257 DMA */
1426 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1427 Name(_CRS, ResourceTemplate() {
1428 DMA(Compatibility,BusMaster,Transfer8){4}
1429 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1430 IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
1431 IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
1432 IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
1433 IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
1434 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1435 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1436 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1438 Device(COPR) {
1439 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1440 Name(_CRS, ResourceTemplate() {
1441 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1442 IRQNoFlags(){13}
1443 })
1444 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1445 #if 0
1446 Device(HPTM) {
1447 Name(_HID,EISAID("PNP0103"))
1448 Name(CRS,ResourceTemplate() {
1449 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1450 })
1451 Method(_STA, 0) {
1452 Return(0x0F) /* sata is visible */
1453 }
1454 Method(_CRS, 0) {
1455 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1456 Store(HPBA, HPBA)
1457 Return(CRS)
1458 }
1459 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1460 #endif
1461 } /* end LIBR */
1463 Device(HPBR) {
1464 Name(_ADR, 0x00140004)
1465 } /* end HostPciBr */
1467 Device(ACAD) {
1468 Name(_ADR, 0x00140005)
1469 } /* end Ac97audio */
1471 Device(ACMD) {
1472 Name(_ADR, 0x00140006)
1473 } /* end Ac97modem */
1475 Name(CRES, ResourceTemplate() {
1476 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1478 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1479 0x0000, /* address granularity */
1480 0x0000, /* range minimum */
1481 0x0CF7, /* range maximum */
1482 0x0000, /* translation */
1483 0x0CF8 /* length */
1484 )
1486 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1487 0x0000, /* address granularity */
1488 0x0D00, /* range minimum */
1489 0xFFFF, /* range maximum */
1490 0x0000, /* translation */
1491 0xF300 /* length */
1492 )
1493 #if 0
1494 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1495 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1496 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1497 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1499 /* DRAM Memory from 1MB to TopMem */
1500 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1502 /* BIOS space just below 4GB */
1503 DWORDMemory(
1504 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1505 0x00, /* Granularity */
1506 0x00000000, /* Min */
1507 0x00000000, /* Max */
1508 0x00000000, /* Translation */
1509 0x00000000, /* Max-Min, RLEN */
1510 ,,
1511 PCBM
1512 )
1514 /* DRAM memory from 4GB to TopMem2 */
1515 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1516 0xFFFFFFFF, /* Granularity */
1517 0x00000000, /* Min */
1518 0x00000000, /* Max */
1519 0x00000000, /* Translation */
1520 0x00000000, /* Max-Min, RLEN */
1521 ,,
1522 DMHI
1523 )
1525 /* BIOS space just below 16EB */
1526 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1527 0xFFFFFFFF, /* Granularity */
1528 0x00000000, /* Min */
1529 0x00000000, /* Max */
1530 0x00000000, /* Translation */
1531 0x00000000, /* Max-Min, RLEN */
1532 ,,
1533 PEBM
1534 )
1535 #endif
1536 /* memory space for PCI BARs below 4GB */
1537 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1538 }) /* End Name(_SB.PCI0.CRES) */
1540 Method(_CRS, 0) {
1541 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1542 #if 0
1543 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1544 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1545 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1546 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1547 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1548 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1550 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1551 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1552 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1553 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1555 If(LGreater(LOMH, 0xC0000)){
1556 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1557 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1558 }
1560 /* Set size of memory from 1MB to TopMem */
1561 Subtract(TOM1, 0x100000, DMLL)
1563 /*
1564 * If(LNotEqual(TOM2, 0x00000000)){
1565 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1566 * Subtract(TOM2, 0x100000000, DMHL)
1567 * }
1568 */
1570 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1571 If(LEqual(TOM2, 0x00000000)){
1572 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1573 Store(PBLN,PBML)
1574 }
1575 Else { /* Otherwise, put the BIOS just below 16EB */
1576 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1577 Store(PBLN,EBML)
1578 }
1579 #endif
1580 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1581 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1582 /*
1583 * Declare memory between TOM1 and 4GB as available
1584 * for PCI MMIO.
1585 * Use ShiftLeft to avoid 64bit constant (for XP).
1586 * This will work even if the OS does 32bit arithmetic, as
1587 * 32bit (0x00000000 - TOM1) will wrap and give the same
1588 * result as 64bit (0x100000000 - TOM1).
1589 */
1590 Store(TOM1, MM1B)
1591 ShiftLeft(0x10000000, 4, Local0)
1592 Subtract(Local0, TOM1, Local0)
1593 Store(Local0, MM1L)
1595 Return(CRES) /* note to change the Name buffer */
1596 } /* end of Method(_SB.PCI0._CRS) */
1598 /*
1599 *
1600 * FIRST METHOD CALLED UPON BOOT
1601 *
1602 * 1. If debugging, print current OS and ACPI interpreter.
1603 * 2. Get PCI Interrupt routing from ACPI VSM, this
1604 * value is based on user choice in BIOS setup.
1605 */
1606 Method(_INI, 0) {
1607 /* DBGO("\\_SB\\_INI\n") */
1608 /* DBGO(" DSDT.ASL code from ") */
1609 /* DBGO(__DATE__) */
1610 /* DBGO(" ") */
1611 /* DBGO(__TIME__) */
1612 /* DBGO("\n Sleep states supported: ") */
1613 /* DBGO("\n") */
1614 /* DBGO(" \\_OS=") */
1615 /* DBGO(\_OS) */
1616 /* DBGO("\n \\_REV=") */
1617 /* DBGO(\_REV) */
1618 /* DBGO("\n") */
1620 /* Determine the OS we're running on */
1621 OSFL()
1623 /* On older chips, clear PciExpWakeDisEn */
1624 /*if (LLessEqual(\SBRI, 0x13)) {
1625 * Store(0,\PWDE)
1626 * }
1627 */
1628 } /* End Method(_SB._INI) */
1629 } /* End Device(PCI0) */
1631 Device(PWRB) { /* Start Power button device */
1632 Name(_HID, EISAID("PNP0C0C"))
1633 Name(_UID, 0xAA)
1634 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1635 Name(_STA, 0x0B) /* sata is invisible */
1636 }
1637 } /* End \_SB scope */
1639 Scope(\_SI) {
1640 Method(_SST, 1) {
1641 /* DBGO("\\_SI\\_SST\n") */
1642 /* DBGO(" New Indicator state: ") */
1643 /* DBGO(Arg0) */
1644 /* DBGO("\n") */
1645 }
1646 } /* End Scope SI */
1647 }
1648 /* End of ASL file */