src/mainboard/aaeon/pfm-540i_revb/irq_tables.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /* Based on irq_tables.c from AMD's DB800 mainboard. */
  18
  19 #include <arch/pirq_routing.h>
  20 #include <console/console.h>
  21 #include <arch/io.h>
  22 #include <arch/pirq_routing.h>
  23 #include "southbridge/amd/cs5536/cs5536.h"
  24
  25 /* Platform IRQs */
  26 #define PIRQA 5
  27 #define PIRQB 11
  28 #define PIRQC 10
  29 #define PIRQD 9
  30
  31 /* Map */
  32 #define M_PIRQA (1 << PIRQA)    /* Bitmap of supported IRQs */
  33 #define M_PIRQB (1 << PIRQB)    /* Bitmap of supported IRQs */
  34 #define M_PIRQC (1 << PIRQC)    /* Bitmap of supported IRQs */
  35 #define M_PIRQD (1 << PIRQD)    /* Bitmap of supported IRQs */
  36
  37 /* Link */
  38 #define L_PIRQA  1              /* Means Slot INTx# Connects To Chipset INTA# */
  39 #define L_PIRQB  2              /* Means Slot INTx# Connects To Chipset INTB# */
  40 #define L_PIRQC  3              /* Means Slot INTx# Connects To Chipset INTC# */
  41 #define L_PIRQD  4              /* Means Slot INTx# Connects To Chipset INTD# */
  42
  43 static const struct irq_routing_table intel_irq_routing_table = {
  44         PIRQ_SIGNATURE,         /* u32 signature */
  45         PIRQ_VERSION,           /* u16 version   */
  46         32 + 16 * CONFIG_IRQ_SLOT_COUNT,  /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
  47         0x00,                   /* Where the interrupt router lies (bus) */
  48         (0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
  49         0x00,                   /* IRQs devoted exclusively to PCI usage */
  50         0x100B,                 /* Vendor */
  51         0x002B,                 /* Device */
  52         0,                      /* Miniport data */
  53         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},      /* u8 rfu[11] */
  54         0x00,                   /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
  55         {
  56           /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
  57           /* bus, dev|fn,           {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
  58           /* CPU */
  59           {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  60           /* Ethernet */
  61           {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  62           /* Chipset */
  63           {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
  64          }
  65 };
  66
  67 unsigned long write_pirq_routing_table(unsigned long addr)
  68 {
  69         return copy_pirq_routing_table(addr, &intel_irq_routing_table);
  70 }