src/include/reg_script.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef REG_SCRIPT_H
  17 #define REG_SCRIPT_H
  18
  19 #include <stdint.h>
  20 #include <arch/io.h>
  21 #include <device/device.h>
  22 #include <device/resource.h>
  23
  24 /*
  25  * The reg script library is a way to provide data-driven I/O accesses for
  26  * initializing devices. It currently supports PCI, legacy I/O,
  27  * memory-mapped I/O, and IOSF accesses.
  28  *
  29  * In order to simplify things for the developer the following features
  30  * are employed:
  31  * - Chaining of tables that allow runtime tables to chain to compile-time
  32  *   tables.
  33  * - Notion of current device (device_t) being worked on. This allows for
  34  *   PCI config, io, and mmio on a particular device's resources.
  35  *
  36  * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
  37  * and pop of the context. A chained reg_script inherits the previous
  38  * context (such as current device), but it does not impact the previous
  39  * context in any way.
  40  */
  41
  42 enum {
  43         REG_SCRIPT_COMMAND_READ,
  44         REG_SCRIPT_COMMAND_WRITE,
  45         REG_SCRIPT_COMMAND_RMW,
  46         REG_SCRIPT_COMMAND_POLL,
  47         REG_SCRIPT_COMMAND_SET_DEV,
  48         REG_SCRIPT_COMMAND_NEXT,
  49         REG_SCRIPT_COMMAND_END,
  50 };
  51
  52 enum {
  53         REG_SCRIPT_TYPE_PCI,
  54         REG_SCRIPT_TYPE_IO,
  55         REG_SCRIPT_TYPE_MMIO,
  56         REG_SCRIPT_TYPE_RES,
  57         REG_SCRIPT_TYPE_IOSF,
  58         REG_SCRIPT_TYPE_MSR,
  59
  60         /* Insert other platform independent values above this comment */
  61
  62         REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000
  63 };
  64
  65 enum {
  66         REG_SCRIPT_SIZE_8,
  67         REG_SCRIPT_SIZE_16,
  68         REG_SCRIPT_SIZE_32,
  69         REG_SCRIPT_SIZE_64,
  70 };
  71
  72 struct reg_script {
  73         uint32_t command;
  74         uint32_t type;
  75         uint32_t size;
  76         uint32_t reg;
  77         uint64_t mask;
  78         uint64_t value;
  79         uint32_t timeout;
  80         union {
  81                 uint32_t id;
  82                 const struct reg_script *next;
  83                 device_t dev;
  84                 unsigned int res_index;
  85         };
  86 };
  87
  88 struct reg_script_context {
  89         device_t dev;
  90         struct resource *res;
  91         const struct reg_script *step;
  92 };
  93
  94 #ifndef __PRE_RAM__
  95 struct reg_script_bus_entry {
  96         int type;
  97         uint64_t (*reg_script_read)(struct reg_script_context *ctx);
  98         void (*reg_script_write)(struct reg_script_context *ctx);
  99 };
 100
 101 /* Get the address and length of the platform bus table */
 102 const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries);
 103
 104 #endif  /* __PRE_RAM */
 105
 106 /* Internal helper Macros. */
 107
 108 #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
 109                           mask_, value_, timeout_, id_)  \
 110         { .command = cmd_,     \
 111           .type = type_,       \
 112           .size = size_,       \
 113           .reg = reg_,         \
 114           .mask = mask_,       \
 115           .value = value_,     \
 116           .timeout = timeout_, \
 117           .id = id_,           \
 118         }
 119
 120 #define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
 121                                mask_, value_, timeout_)  \
 122         { .command = cmd_,         \
 123           .type = type_,           \
 124           .size = size_,           \
 125           .reg = reg_,             \
 126           .mask = mask_,           \
 127           .value = value_,         \
 128           .timeout = timeout_,     \
 129           .res_index = res_index_, \
 130         }
 131
 132 /*
 133  * PCI
 134  */
 135
 136 #define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
 137         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,          \
 138                                REG_SCRIPT_TYPE_PCI,                \
 139                                REG_SCRIPT_SIZE_##bits_,            \
 140                                reg_, mask_, value_, timeout_, 0)
 141 #define REG_PCI_READ8(reg_) \
 142         REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
 143 #define REG_PCI_READ16(reg_) \
 144         REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
 145 #define REG_PCI_READ32(reg_) \
 146         REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
 147 #define REG_PCI_WRITE8(reg_, value_) \
 148         REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
 149 #define REG_PCI_WRITE16(reg_, value_) \
 150         REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
 151 #define REG_PCI_WRITE32(reg_, value_) \
 152         REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
 153 #define REG_PCI_RMW8(reg_, mask_, value_) \
 154         REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
 155 #define REG_PCI_RMW16(reg_, mask_, value_) \
 156         REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
 157 #define REG_PCI_RMW32(reg_, mask_, value_) \
 158         REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
 159 #define REG_PCI_OR8(reg_, value_) \
 160         REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
 161 #define REG_PCI_OR16(reg_, value_) \
 162         REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
 163 #define REG_PCI_OR32(reg_, value_) \
 164         REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
 165 #define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
 166         REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
 167 #define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
 168         REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
 169 #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
 170         REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
 171
 172 /*
 173  * Legacy IO
 174  */
 175
 176 #define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
 177         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,         \
 178                                REG_SCRIPT_TYPE_IO,                \
 179                                REG_SCRIPT_SIZE_##bits_,           \
 180                                reg_, mask_, value_, timeout_, 0)
 181 #define REG_IO_READ8(reg_) \
 182         REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
 183 #define REG_IO_READ16(reg_) \
 184         REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
 185 #define REG_IO_READ32(reg_) \
 186         REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
 187 #define REG_IO_WRITE8(reg_, value_) \
 188         REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
 189 #define REG_IO_WRITE16(reg_, value_) \
 190         REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
 191 #define REG_IO_WRITE32(reg_, value_) \
 192         REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
 193 #define REG_IO_RMW8(reg_, mask_, value_) \
 194         REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
 195 #define REG_IO_RMW16(reg_, mask_, value_) \
 196         REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
 197 #define REG_IO_RMW32(reg_, mask_, value_) \
 198         REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
 199 #define REG_IO_OR8(reg_, value_) \
 200         REG_IO_RMW8(reg_, 0xff, value_)
 201 #define REG_IO_OR16(reg_, value_) \
 202         REG_IO_RMW16(reg_, 0xffff, value_)
 203 #define REG_IO_OR32(reg_, value_) \
 204         REG_IO_RMW32(reg_, 0xffffffff, value_)
 205 #define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
 206         REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
 207 #define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
 208         REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
 209 #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
 210         REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
 211
 212 /*
 213  * Memory Mapped IO
 214  */
 215
 216 #define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
 217         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,           \
 218                                REG_SCRIPT_TYPE_MMIO,                \
 219                                REG_SCRIPT_SIZE_##bits_,             \
 220                                reg_, mask_, value_, timeout_, 0)
 221 #define REG_MMIO_READ8(reg_) \
 222         REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
 223 #define REG_MMIO_READ16(reg_) \
 224         REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
 225 #define REG_MMIO_READ32(reg_) \
 226         REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
 227 #define REG_MMIO_WRITE8(reg_, value_) \
 228         REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
 229 #define REG_MMIO_WRITE16(reg_, value_) \
 230         REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
 231 #define REG_MMIO_WRITE32(reg_, value_) \
 232         REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
 233 #define REG_MMIO_RMW8(reg_, mask_, value_) \
 234         REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
 235 #define REG_MMIO_RMW16(reg_, mask_, value_) \
 236         REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
 237 #define REG_MMIO_RMW32(reg_, mask_, value_) \
 238         REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
 239 #define REG_MMIO_OR8(reg_, value_) \
 240         REG_MMIO_RMW8(reg_, 0xff, value_)
 241 #define REG_MMIO_OR16(reg_, value_) \
 242         REG_MMIO_RMW16(reg_, 0xffff, value_)
 243 #define REG_MMIO_OR32(reg_, value_) \
 244         REG_MMIO_RMW32(reg_, 0xffffffff, value_)
 245 #define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
 246         REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
 247 #define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
 248         REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
 249 #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
 250         REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
 251
 252 /*
 253  * Access through a device's resource such as a Base Address Register (BAR)
 254  */
 255
 256 #define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
 257         _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_,                \
 258                                REG_SCRIPT_TYPE_RES, bar_,                \
 259                                REG_SCRIPT_SIZE_##bits_,                  \
 260                                reg_, mask_, value_, timeout_)
 261 #define REG_RES_READ8(bar_, reg_) \
 262         REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
 263 #define REG_RES_READ16(bar_, reg_) \
 264         REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
 265 #define REG_RES_READ32(bar_, reg_) \
 266         REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
 267 #define REG_RES_WRITE8(bar_, reg_, value_) \
 268         REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
 269 #define REG_RES_WRITE16(bar_, reg_, value_) \
 270         REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
 271 #define REG_RES_WRITE32(bar_, reg_, value_) \
 272         REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
 273 #define REG_RES_RMW8(bar_, reg_, mask_, value_) \
 274         REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
 275 #define REG_RES_RMW16(bar_, reg_, mask_, value_) \
 276         REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
 277 #define REG_RES_RMW32(bar_, reg_, mask_, value_) \
 278         REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
 279 #define REG_RES_OR8(bar_, reg_, value_) \
 280         REG_RES_RMW8(bar_, reg_, 0xff, value_)
 281 #define REG_RES_OR16(bar_, reg_, value_) \
 282         REG_RES_RMW16(bar_, reg_, 0xffff, value_)
 283 #define REG_RES_OR32(bar_, reg_, value_) \
 284         REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
 285 #define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
 286         REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
 287 #define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
 288         REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
 289 #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
 290         REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
 291
 292
 293 #if CONFIG_SOC_INTEL_BAYTRAIL
 294 /*
 295  * IO Sideband Function
 296  */
 297
 298 #define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
 299         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,      \
 300                                REG_SCRIPT_TYPE_IOSF,           \
 301                                REG_SCRIPT_SIZE_32,             \
 302                                reg_, mask_, value_, timeout_, unit_)
 303 #define REG_IOSF_READ(unit_, reg_) \
 304         REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
 305 #define REG_IOSF_WRITE(unit_, reg_, value_) \
 306         REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
 307 #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
 308         REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
 309 #define REG_IOSF_OR(unit_, reg_, value_) \
 310         REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
 311 #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
 312         REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
 313 #endif  /* CONFIG_SOC_INTEL_BAYTRAIL */
 314
 315 /*
 316  * CPU Model Specific Register
 317  */
 318
 319 #define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
 320         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,   \
 321                                REG_SCRIPT_TYPE_MSR,         \
 322                                REG_SCRIPT_SIZE_64,          \
 323                                reg_, mask_, value_, timeout_, 0)
 324 #define REG_MSR_READ(reg_) \
 325         REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
 326 #define REG_MSR_WRITE(reg_, value_) \
 327         REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
 328 #define REG_MSR_RMW(reg_, mask_, value_) \
 329         REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
 330 #define REG_MSR_OR(reg_, value_) \
 331         REG_MSR_RMW(reg_, -1ULL, value_)
 332 #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
 333         REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
 334
 335 /*
 336  * Chain to another table.
 337  */
 338 #define REG_SCRIPT_NEXT(next_)                \
 339         { .command = REG_SCRIPT_COMMAND_NEXT, \
 340           .next = next_,                      \
 341         }
 342
 343 /*
 344  * Set current device
 345  */
 346 #define REG_SCRIPT_SET_DEV(dev_)                 \
 347         { .command = REG_SCRIPT_COMMAND_SET_DEV, \
 348           .dev = dev_,                           \
 349         }
 350
 351 /*
 352  * Last script entry. All tables need to end with REG_SCRIPT_END.
 353  */
 354 #define REG_SCRIPT_END \
 355         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
 356
 357 void reg_script_run(const struct reg_script *script);
 358 void reg_script_run_on_dev(device_t dev, const struct reg_script *step);
 359
 360 #endif /* REG_SCRIPT_H */