src/include/cpu/x86/cache.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Eric W. Biederman
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef CPU_X86_CACHE
  17 #define CPU_X86_CACHE
  18
  19 #include <cpu/x86/cr.h>
  20
  21 #define CR0_CacheDisable        (CR0_CD)
  22 #define CR0_NoWriteThrough      (CR0_NW)
  23
  24 #if !defined(__ASSEMBLER__)
  25
  26 /*
  27  * Need two versions because ROMCC chokes on certain clobbers:
  28  * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:
  29  * 0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
  30  */
  31
  32 #if defined(__GNUC__)
  33
  34 static inline void wbinvd(void)
  35 {
  36         asm volatile ("wbinvd" ::: "memory");
  37 }
  38
  39 #else
  40
  41 static inline void wbinvd(void)
  42 {
  43         asm volatile ("wbinvd");
  44 }
  45
  46 #endif
  47
  48 static inline void invd(void)
  49 {
  50         asm volatile("invd" ::: "memory");
  51 }
  52
  53 /* The following functions require the always_inline due to AMD
  54  * function STOP_CAR_AND_CPU that disables cache as
  55  * ram, the cache as ram stack can no longer be used. Called
  56  * functions must be inlined to avoid stack usage. Also, the
  57  * compiler must keep local variables register based and not
  58  * allocated them from the stack. With gcc 4.5.0, some functions
  59  * declared as inline are not being inlined. This patch forces
  60  * these functions to always be inlined by adding the qualifier
  61  * __attribute__((always_inline)) to their declaration.
  62  */
  63 static inline __attribute__((always_inline)) void enable_cache(void)
  64 {
  65         unsigned long cr0;
  66         cr0 = read_cr0();
  67         cr0 &= ~(CR0_CD | CR0_NW);
  68         write_cr0(cr0);
  69 }
  70
  71 static inline __attribute__((always_inline)) void disable_cache(void)
  72 {
  73         /* Disable and write back the cache */
  74         unsigned long cr0;
  75         cr0 = read_cr0();
  76         cr0 |= CR0_CD;
  77         wbinvd();
  78         write_cr0(cr0);
  79         wbinvd();
  80 }
  81
  82 #if !defined(__PRE_RAM__)
  83 void x86_enable_cache(void);
  84 #endif
  85
  86 #endif /* !__ASSEMBLER__ */
  87 #endif /* CPU_X86_CACHE */