src/include/cpu/intel/speedstep.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *               2012 secunet Security Networks AG
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #ifndef CPU_INTEL_SPEEDSTEP_H
  19 #define CPU_INTEL_SPEEDSTEP_H
  20
  21 #include <stdint.h>
  22
  23 /* Magic value used to locate speedstep configuration in the device tree */
  24 #define SPEEDSTEP_APIC_MAGIC 0xACAC
  25
  26 /* MWAIT coordination I/O base address. This must match
  27  * the \_PR_.CP00 PM base address.
  28  */
  29 #define PMB0_BASE 0x510
  30
  31 /* PMB1: I/O port that triggers SMI once cores are in the same state.
  32  * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
  33  */
  34 #define PMB1_BASE 0x800
  35
  36
  37 /* Speedstep related MSRs */
  38 #define IA32_PLATFORM_ID  0x017
  39 #define IA32_PERF_STS     0x198
  40 #define IA32_PERF_CTL     0x199
  41 #define MSR_THERM2_CTL    0x19D
  42 #define IA32_MISC_ENABLES 0x1A0
  43 #define MSR_FSB_FREQ            0xcd
  44 #define MSR_FSB_CLOCK_VCC       0xce
  45 #define MSR_PMG_CST_CONFIG_CONTROL      0xe2
  46 #define MSR_PMG_IO_BASE_ADDR    0xe3
  47 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4
  48 #define MSR_EXTENDED_CONFIG     0xee
  49
  50
  51 typedef struct {
  52         uint8_t dynfsb : 1; /* whether this is SLFM */
  53         uint8_t nonint : 1; /* add .5 to ratio */
  54         uint8_t ratio : 6;
  55         uint8_t vid;
  56         uint8_t is_turbo;
  57         uint8_t is_slfm;
  58         uint32_t power;
  59 } sst_state_t;
  60 #define SPEEDSTEP_RATIO_SHIFT           8
  61 #define SPEEDSTEP_RATIO_DYNFSB_SHIFT    (7 + SPEEDSTEP_RATIO_SHIFT)
  62 #define SPEEDSTEP_RATIO_DYNFSB          (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
  63 #define SPEEDSTEP_RATIO_NONINT_SHIFT    (6 + SPEEDSTEP_RATIO_SHIFT)
  64 #define SPEEDSTEP_RATIO_NONINT          (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
  65 #define SPEEDSTEP_RATIO_VALUE_MASK      (0x1f << SPEEDSTEP_RATIO_SHIFT)
  66 #define SPEEDSTEP_VID_MASK              0x3f
  67 #define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){             \
  68                 0, /* dynfsb won't be read. */                          \
  69                 ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0,        \
  70                 (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK)            \
  71                                         >> SPEEDSTEP_RATIO_SHIFT),      \
  72                 (val & mask) & SPEEDSTEP_VID_MASK,                      \
  73                 0, /* not turbo by default */                           \
  74                 0, /* not slfm by default */                            \
  75                 0  /* power is hardcoded in software. */                \
  76         })
  77 #define SPEEDSTEP_ENCODE_STATE(state)   (                               \
  78         ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) |    \
  79         ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) |    \
  80         ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) |            \
  81         ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
  82 #define SPEEDSTEP_DOUBLE_RATIO(state)   (                               \
  83         ((uint8_t)(state).ratio * 2) + (state).nonint)
  84
  85 typedef struct {
  86         sst_state_t slfm;
  87         sst_state_t min;
  88         sst_state_t max;
  89         sst_state_t turbo;
  90 } sst_params_t;
  91
  92 /* Looking at core2's spec, the highest normal bus ratio for an eist enabled
  93    processor is 14, the lowest is always 6. This makes 5 states with the
  94    minimal step width of 2. With turbo mode and super LFM we have at most 7. */
  95 #define SPEEDSTEP_MAX_NORMAL_STATES     5
  96 #define SPEEDSTEP_MAX_STATES            (SPEEDSTEP_MAX_NORMAL_STATES + 2)
  97 typedef struct {
  98         /* Table of p-states for EMTTM and ACPI by decreasing performance. */
  99         sst_state_t states[SPEEDSTEP_MAX_STATES];
 100         int num_states;
 101 } sst_table_t;
 102
 103 void speedstep_gen_pstates(sst_table_t *);
 104
 105 #define SPEEDSTEP_MAX_POWER_YONAH       31000
 106 #define SPEEDSTEP_MIN_POWER_YONAH       13100
 107 #define SPEEDSTEP_MAX_POWER_MEROM       35000
 108 #define SPEEDSTEP_MIN_POWER_MEROM       25000
 109 #define SPEEDSTEP_SLFM_POWER_MEROM      12000
 110 #define SPEEDSTEP_MAX_POWER_PENRYN      35000
 111 #define SPEEDSTEP_MIN_POWER_PENRYN      15000
 112 #define SPEEDSTEP_SLFM_POWER_PENRYN     12000
 113
 114 #endif /* CPU_INTEL_SPEEDSTEP_H */