src/device/dram/ddr3.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011-2013  Alexandru Gagniuc <mr.nuke.me@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /**
  18  * @file ddr3.c
  19  *
  20  * \brief Utilities for decoding DDR3 SPDs
  21  */
  22
  23 #include <console/console.h>
  24 #include <device/device.h>
  25 #include <device/dram/ddr3.h>
  26
  27 /*==============================================================================
  28  * = DDR3 SPD decoding helpers
  29  *----------------------------------------------------------------------------*/
  30
  31 /**
  32  * \brief Checks if the DIMM is Registered based on byte[3] of the SPD
  33  *
  34  * Tells if the DIMM type is registered or not.
  35  *
  36  * @param type DIMM type. This is byte[3] of the SPD.
  37  */
  38 int dimm_is_registered(enum spd_dimm_type type)
  39 {
  40         if ((type == SPD_DIMM_TYPE_RDIMM)
  41             | (type == SPD_DIMM_TYPE_MINI_RDIMM)
  42             | (type == SPD_DIMM_TYPE_72B_SO_RDIMM))
  43                 return 1;
  44
  45         return 0;
  46 }
  47
  48 /**
  49  * \brief Calculate the CRC of a DDR3 SPD
  50  *
  51  * @param spd pointer to raw SPD data
  52  * @param len length of data in SPD
  53  *
  54  * @return the CRC of the SPD data, or 0 when spd data is truncated.
  55  */
  56 u16 spd_ddr3_calc_crc(u8 *spd, int len)
  57 {
  58         int n_crc, i;
  59         u8 *ptr;
  60         u16 crc;
  61
  62         /* Find the number of bytes covered by CRC */
  63         if (spd[0] & 0x80) {
  64                 n_crc = 117;
  65         } else {
  66                 n_crc = 126;
  67         }
  68
  69         if (len < n_crc)
  70                 /* Not enough bytes available to get the CRC */
  71                 return 0;
  72
  73         /* Compute the CRC */
  74         crc = 0;
  75         ptr = spd;
  76         while (--n_crc >= 0) {
  77                 crc = crc ^ (int)*ptr++ << 8;
  78                 for (i = 0; i < 8; ++i)
  79                         if (crc & 0x8000) {
  80                                 crc = crc << 1 ^ 0x1021;
  81                         } else {
  82                                 crc = crc << 1;
  83                         }
  84         }
  85         return crc;
  86 }
  87
  88 /**
  89  * \brief Decode the raw SPD data
  90  *
  91  * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a
  92  * @ref dimm_attr structure. The SPD data must first be read in a contiguous
  93  * array, and passed to this function.
  94  *
  95  * @param dimm pointer to @ref dimm_attr structure where the decoded data is to
  96  *             be stored
  97  * @param spd array of raw data previously read from the SPD.
  98  *
  99  * @return @ref spd_status enumerator
 100  *              SPD_STATUS_OK -- decoding was successful
 101  *              SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD
 102  *              SPD_STATUS_CRC_ERROR -- CRC did not verify
 103  *              SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
 104  *                                          detected.
 105  */
 106 int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
 107 {
 108         int ret;
 109         u16 crc, spd_crc;
 110         u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width;
 111         u8 reg8;
 112         u32 mtb;                /* medium time base */
 113         unsigned int val, param;
 114
 115         ret = SPD_STATUS_OK;
 116
 117         /* Don't assume we memset 0 dimm struct. Clear all our flags */
 118         dimm->flags.raw = 0;
 119         /* Make sure that the SPD dump is indeed from a DDR3 module */
 120         if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) {
 121                 printram("Not a DDR3 SPD!\n");
 122                 dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 123                 return SPD_STATUS_INVALID;
 124         }
 125         dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3;
 126         dimm->dimm_type = spd[3] & 0xf;
 127
 128         crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data));
 129         /* Compare with the CRC in the SPD */
 130         spd_crc = (spd[127] << 8) + spd[126];
 131         /* Verify the CRC is correct */
 132         if (crc != spd_crc) {
 133                 printram("ERROR: SPD CRC failed!!!\n");
 134                 ret = SPD_STATUS_CRC_ERROR;
 135         };
 136
 137         printram("  Revision: %x\n", spd[1]);
 138         printram("  Type    : %x\n", spd[2]);
 139         printram("  Key     : %x\n", spd[3]);
 140
 141         reg8 = spd[4];
 142         /* Number of memory banks */
 143         val = (reg8 >> 4) & 0x07;
 144         if (val > 0x03) {
 145                 printram("  Invalid number of memory banks\n");
 146                 ret = SPD_STATUS_INVALID_FIELD;
 147         }
 148         param = 1 << (val + 3);
 149         printram("  Banks   : %u\n", param);
 150         /* SDRAM capacity */
 151         capacity_shift = reg8 & 0x0f;
 152         if (capacity_shift > 0x06) {
 153                 printram("  Invalid module capacity\n");
 154                 ret = SPD_STATUS_INVALID_FIELD;
 155         }
 156         if (capacity_shift < 0x02) {
 157                 printram("  Capacity: %u Mb\n", 256 << capacity_shift);
 158         } else {
 159                 printram("  Capacity: %u Gb\n", 1 << (capacity_shift - 2));
 160         }
 161
 162         reg8 = spd[5];
 163         /* Row address bits */
 164         val = (reg8 >> 3) & 0x07;
 165         if (val > 0x04) {
 166                 printram("  Invalid row address bits\n");
 167                 ret = SPD_STATUS_INVALID_FIELD;
 168         }
 169         dimm->row_bits = val + 12;
 170         /* Column address bits */
 171         val = reg8 & 0x07;
 172         if (val > 0x03) {
 173                 printram("  Invalid column address bits\n");
 174                 ret = SPD_STATUS_INVALID_FIELD;
 175         }
 176         dimm->col_bits = val + 9;
 177
 178         /* Module nominal voltage */
 179         reg8 = spd[6];
 180         printram("  Supported voltages:");
 181         if (reg8 & (1 << 2)) {
 182                 dimm->flags.operable_1_25V = 1;
 183                 printram(" 1.25V");
 184         }
 185         if (reg8 & (1 << 1)) {
 186                 dimm->flags.operable_1_35V = 1;
 187                 printram(" 1.35V");
 188         }
 189         if (!(reg8 & (1 << 0))) {
 190                 dimm->flags.operable_1_50V = 1;
 191                 printram(" 1.5V");
 192         }
 193         printram("\n");
 194
 195         /* Module organization */
 196         reg8 = spd[7];
 197         /* Number of ranks */
 198         val = (reg8 >> 3) & 0x07;
 199         if (val > 3) {
 200                 printram("  Invalid number of ranks\n");
 201                 ret = SPD_STATUS_INVALID_FIELD;
 202         }
 203         dimm->ranks = val + 1;
 204         /* SDRAM device width */
 205         val = (reg8 & 0x07);
 206         if (val > 3) {
 207                 printram("  Invalid SDRAM width\n");
 208                 ret = SPD_STATUS_INVALID_FIELD;
 209         }
 210         dimm->width = (4 << val);
 211         printram("  SDRAM width       : %u\n", dimm->width);
 212
 213         /* Memory bus width */
 214         reg8 = spd[8];
 215         /* Bus extension */
 216         val = (reg8 >> 3) & 0x03;
 217         if (val > 1) {
 218                 printram("  Invalid bus extension\n");
 219                 ret = SPD_STATUS_INVALID_FIELD;
 220         }
 221         dimm->flags.is_ecc = val ? 1 : 0;
 222         printram("  Bus extension     : %u bits\n", val ? 8 : 0);
 223         /* Bus width */
 224         val = reg8 & 0x07;
 225         if (val > 3) {
 226                 printram("  Invalid bus width\n");
 227                 ret = SPD_STATUS_INVALID_FIELD;
 228         }
 229         bus_width = 8 << val;
 230         printram("  Bus width         : %u\n", bus_width);
 231
 232         /* We have all the info we need to compute the dimm size */
 233         /* Capacity is 256Mbit multiplied by the power of 2 specified in
 234          * capacity_shift
 235          * The rest is the JEDEC formula */
 236         dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width
 237                          * dimm->ranks) / dimm->width;
 238
 239         /* Fine Timebase (FTB) Dividend/Divisor */
 240         /* Dividend */
 241         ftb_dividend = (spd[9] >> 4) & 0x0f;
 242         /* Divisor */
 243         ftb_divisor = spd[9] & 0x0f;
 244
 245         /* Medium Timebase =
 246          *   Medium Timebase (MTB) Dividend /
 247          *   Medium Timebase (MTB) Divisor */
 248         mtb = (((u32) spd[10]) << 8) / spd[11];
 249
 250         /* SDRAM Minimum Cycle Time (tCKmin) */
 251         dimm->tCK = spd[12] * mtb;
 252         /* CAS Latencies Supported */
 253         dimm->cas_supported = (spd[15] << 8) + spd[14];
 254         /* Minimum CAS Latency Time (tAAmin) */
 255         dimm->tAA = spd[16] * mtb;
 256         /* Minimum Write Recovery Time (tWRmin) */
 257         dimm->tWR = spd[17] * mtb;
 258         /* Minimum RAS# to CAS# Delay Time (tRCDmin) */
 259         dimm->tRCD = spd[18] * mtb;
 260         /* Minimum Row Active to Row Active Delay Time (tRRDmin) */
 261         dimm->tRRD = spd[19] * mtb;
 262         /* Minimum Row Precharge Delay Time (tRPmin) */
 263         dimm->tRP = spd[20] * mtb;
 264         /* Minimum Active to Precharge Delay Time (tRASmin) */
 265         dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb;
 266         /* Minimum Active to Active/Refresh Delay Time (tRCmin) */
 267         dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb;
 268         /* Minimum Refresh Recovery Delay Time (tRFCmin) */
 269         dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb;
 270         /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */
 271         dimm->tWTR = spd[26] * mtb;
 272         /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
 273         dimm->tRTP = spd[27] * mtb;
 274         /* Minimum Four Activate Window Delay Time (tFAWmin) */
 275         dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb;
 276
 277         /* SDRAM Optional Features */
 278         reg8 = spd[30];
 279         printram("  Optional features :");
 280         if (reg8 & 0x80) {
 281                 dimm->flags.dll_off_mode = 1;
 282                 printram(" DLL-Off_mode");
 283         }
 284         if (reg8 & 0x02) {
 285                 dimm->flags.rzq7_supported = 1;
 286                 printram(" RZQ/7");
 287         }
 288         if (reg8 & 0x01) {
 289                 dimm->flags.rzq6_supported = 1;
 290                 printram(" RZQ/6");
 291         }
 292         printram("\n");
 293
 294         /* SDRAM Thermal and Refresh Options */
 295         reg8 = spd[31];
 296         printram("  Thermal features  :");
 297         if (reg8 & 0x80) {
 298                 dimm->flags.pasr = 1;
 299                 printram(" PASR");
 300         }
 301         if (reg8 & 0x08) {
 302                 dimm->flags.odts = 1;
 303                 printram(" ODTS");
 304         }
 305         if (reg8 & 0x04) {
 306                 dimm->flags.asr = 1;
 307                 printram(" ASR");
 308         }
 309         if (reg8 & 0x02) {
 310                 dimm->flags.ext_temp_range = 1;
 311                 printram(" ext_temp_refresh");
 312         }
 313         if (reg8 & 0x01) {
 314                 dimm->flags.ext_temp_refresh = 1;
 315                 printram(" ext_temp_range");
 316         }
 317         printram("\n");
 318
 319         /*  Module Thermal Sensor */
 320         reg8 = spd[32];
 321         if (reg8 & 0x80)
 322                 dimm->flags.therm_sensor = 1;
 323         printram("  Thermal sensor    : %s\n",
 324                  dimm->flags.therm_sensor ? "yes" : "no");
 325
 326         /*  SDRAM Device Type */
 327         reg8 = spd[33];
 328         printram("  Standard SDRAM    : %s\n", (reg8 & 0x80) ? "no" : "yes");
 329
 330         if (spd[63] & 0x01) {
 331                 dimm->flags.pins_mirrored = 1;
 332                 printram("  DIMM Rank1 Address bits mirrored!!!\n");
 333         }
 334
 335         dimm->reference_card = spd[62] & 0x1f;
 336         printram("  DIMM Reference card %c\n", 'A' + dimm->reference_card);
 337
 338         return ret;
 339 }
 340
 341 /*
 342  * The information printed below has a more informational character, and is not
 343  * necessarily tied in to RAM init debugging. Hence, we stop using printram(),
 344  * and use the standard printk()'s below.
 345  */
 346
 347 static void print_ns(const char *msg, u32 val)
 348 {
 349         u32 mant, fp;
 350         mant = val / 256;
 351         fp = (val % 256) * 1000 / 256;
 352
 353         printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp);
 354 }
 355
 356 /**
 357 * \brief Print the info in DIMM
 358 *
 359 * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is
 360 * selected, or for a purely informative output.
 361 *
 362 * @param dimm pointer to already decoded @ref dimm_attr structure
 363 */
 364 void dram_print_spd_ddr3(const dimm_attr * dimm)
 365 {
 366         u16 val16;
 367         int i;
 368
 369         printk(BIOS_INFO, "  Row    addr bits  : %u\n", dimm->row_bits);
 370         printk(BIOS_INFO, "  Column addr bits  : %u\n", dimm->col_bits);
 371         printk(BIOS_INFO, "  Number of ranks   : %u\n", dimm->ranks);
 372         printk(BIOS_INFO, "  DIMM Capacity     : %u MB\n", dimm->size_mb);
 373
 374         /* CAS Latencies Supported */
 375         val16 = dimm->cas_supported;
 376         printk(BIOS_INFO, "  CAS latencies     :");
 377         i = 0;
 378         do {
 379                 if (val16 & 1)
 380                         printk(BIOS_INFO, " %u", i + 4);
 381                 i++;
 382                 val16 >>= 1;
 383         } while (val16);
 384         printk(BIOS_INFO, "\n");
 385
 386         print_ns("  tCKmin            : ", dimm->tCK);
 387         print_ns("  tAAmin            : ", dimm->tAA);
 388         print_ns("  tWRmin            : ", dimm->tWR);
 389         print_ns("  tRCDmin           : ", dimm->tRCD);
 390         print_ns("  tRRDmin           : ", dimm->tRRD);
 391         print_ns("  tRPmin            : ", dimm->tRP);
 392         print_ns("  tRASmin           : ", dimm->tRAS);
 393         print_ns("  tRCmin            : ", dimm->tRC);
 394         print_ns("  tRFCmin           : ", dimm->tRFC);
 395         print_ns("  tWTRmin           : ", dimm->tWTR);
 396         print_ns("  tRTPmin           : ", dimm->tRTP);
 397         print_ns("  tFAWmin           : ", dimm->tFAW);
 398 }
 399
 400 /*==============================================================================
 401  *= DDR3 MRS helpers
 402  *----------------------------------------------------------------------------*/
 403
 404 /*
 405  * MRS command structure:
 406  * cmd[15:0] = Address pins MA[15:0]
 407  * cmd[18:16] = Bank address BA[2:0]
 408  */
 409
 410 /* Map tWR value to a bitmask of the MR0 cycle */
 411 static u16 ddr3_twr_to_mr0_map(u8 twr)
 412 {
 413         if ((twr >= 5) && (twr <= 8))
 414                 return (twr - 4) << 9;
 415
 416         /*
 417          * From 8T onwards, we can only use even values. Round up if we are
 418          * given an odd value.
 419          */
 420         if ((twr >= 9) && (twr <= 14))
 421                 return ((twr + 1) >> 1) << 9;
 422
 423         /* tWR == 16T is [000] */
 424         return 0;
 425 }
 426
 427 /* Map the CAS latency to a bitmask for the MR0 cycle */
 428 static u16 ddr3_cas_to_mr0_map(u8 cas)
 429 {
 430         u16 mask = 0;
 431         /* A[6:4] are bits [2:0] of (CAS - 4) */
 432         mask = ((cas - 4) & 0x07) << 4;
 433
 434         /* A2 is the MSB of (CAS - 4) */
 435         if ((cas - 4) & (1 << 3))
 436                 mask |= (1 << 2);
 437
 438         return mask;
 439 }
 440
 441 /**
 442  * \brief Get command address for a DDR3 MR0 command
 443  *
 444  * The DDR3 specification only covers odd write_recovery up to 7T. If an odd
 445  * write_recovery greater than 7 is specified, it will be rounded up. If a tWR
 446  * greater than 8 is specified, it is recommended to explicitly round it up or
 447  * down before calling this function.
 448  *
 449  * write_recovery and cas are given in clock cycles. For example, a CAS of 7T
 450  * should be given as 7.
 451  *
 452  * @param precharge_pd
 453  * @param write_recovery Write recovery latency, tWR in clock cycles.
 454  * @param dll_reset
 455  * @param mode
 456  * @param cas CAS latency in clock cycles.
 457  * @param burst_type
 458  * @param burst_length
 459  */
 460 mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd,
 461                        u8 write_recovery,
 462                        enum ddr3_mr0_dll_reset dll_reset,
 463                        enum ddr3_mr0_mode mode,
 464                        u8 cas,
 465                        enum ddr3_mr0_burst_type burst_type,
 466                        enum ddr3_mr0_burst_length burst_length)
 467 {
 468         mrs_cmd_t cmd = 0 << 16;
 469
 470         if (precharge_pd == DDR3_MR0_PRECHARGE_FAST)
 471                 cmd |= (1 << 12);
 472
 473         cmd |= ddr3_twr_to_mr0_map(write_recovery);
 474
 475         if (dll_reset == DDR3_MR0_DLL_RESET_YES)
 476                 cmd |= (1 << 8);
 477
 478         if (mode == DDR3_MR0_MODE_TEST)
 479                 cmd |= (1 << 7);
 480
 481         cmd |= ddr3_cas_to_mr0_map(cas);
 482
 483         if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED)
 484                 cmd |= (1 << 3);
 485
 486         cmd |= (burst_length & 0x03) << 0;
 487
 488         return cmd;
 489 }
 490
 491 static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom)
 492 {
 493         u16 mask = 0;
 494         /* A9 <-> rtt_nom[2] */
 495         if (rtt_nom & (1 << 2))
 496                 mask |= (1 << 9);
 497         /* A6 <-> rtt_nom[1] */
 498         if (rtt_nom & (1 << 1))
 499                 mask |= (1 << 6);
 500         /* A2 <-> rtt_nom[0] */
 501         if (rtt_nom & (1 << 0))
 502                 mask |= (1 << 2);
 503
 504         return mask;
 505 }
 506
 507 static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods)
 508 {
 509         u16 mask = 0;
 510         /* A5 <-> ods[1] */
 511         if (ods & (1 << 1))
 512                 mask |= (1 << 5);
 513         /* A1 <-> ods[0] */
 514         if (ods & (1 << 0))
 515                 mask |= (1 << 1);
 516
 517         return mask;
 518 }
 519
 520 /**
 521  * \brief Get command address for a DDR3 MR1 command
 522  */
 523 mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff,
 524                        enum ddr3_mr1_tqds tqds,
 525                        enum ddr3_mr1_rtt_nom rtt_nom,
 526                        enum ddr3_mr1_write_leveling write_leveling,
 527                        enum ddr3_mr1_ods ods,
 528                        enum ddr3_mr1_additive_latency additive_latency,
 529                        enum ddr3_mr1_dll dll_disable)
 530 {
 531         mrs_cmd_t cmd = 1 << 16;
 532
 533         if (qoff == DDR3_MR1_QOFF_DISABLE)
 534                 cmd |= (1 << 12);
 535
 536         if (tqds == DDR3_MR1_TQDS_ENABLE)
 537                 cmd |= (1 << 11);
 538
 539         cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom);
 540
 541         if (write_leveling == DDR3_MR1_WRLVL_ENABLE)
 542                 cmd |= (1 << 7);
 543
 544         cmd |= ddr3_ods_to_mr1_map(ods);
 545
 546         cmd |= (additive_latency & 0x03) << 3;
 547
 548         if (dll_disable == DDR3_MR1_DLL_DISABLE)
 549                 cmd |= (1 << 0);
 550
 551         return cmd;
 552 }
 553
 554 /**
 555  * \brief Get command address for a DDR3 MR2 command
 556  *
 557  * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be
 558  * given as 7.
 559  *
 560  * @param rtt_wr
 561  * @param extended_temp
 562  * @param self_refresh
 563  * @param cas_cwl CAS write latency in clock cycles.
 564  */
 565
 566 mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr,
 567                        enum ddr3_mr2_srt_range extended_temp,
 568                        enum ddr3_mr2_asr self_refresh, u8 cas_cwl)
 569 {
 570         mrs_cmd_t cmd = 2 << 16;
 571
 572         cmd |= (rtt_wr & 0x03) << 9;
 573
 574         if (extended_temp == DDR3_MR2_SRT_EXTENDED)
 575                 cmd |= (1 << 7);
 576
 577         if (self_refresh == DDR3_MR2_ASR_AUTO)
 578                 cmd |= (1 << 6);
 579
 580         cmd |= ((cas_cwl - 5) & 0x07) << 3;
 581
 582         return cmd;
 583 }
 584
 585 /**
 586  * \brief Get command address for a DDR3 MR3 command
 587  *
 588  * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read
 589  *                          leveling mode. Zero for normal operation.
 590  */
 591 mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr)
 592 {
 593         mrs_cmd_t cmd = 3 << 16;
 594
 595         if (dataflow_from_mpr)
 596                 cmd |= (1 << 2);
 597
 598         return cmd;
 599 }
 600
 601 /**
 602  * \brief Mirror the address bits for this MRS command
 603  *
 604  * Swap the following bits in the MRS command:
 605  *      - MA3 <-> MA4
 606  *      - MA5 <-> MA6
 607  *      - MA7 <-> MA8
 608  *      - BA0 <-> BA1
 609  */
 610 mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd)
 611 {
 612         u32 downshift, upshift;
 613         /* High bits=    A4    |    A6    |    A8    |    BA1 */
 614         /* Low bits =    A3    |    A5    |    A7    |    BA0 */
 615         u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16);
 616         downshift = (cmd & (lowbits << 1));
 617         upshift = (cmd & lowbits);
 618         cmd &= ~(lowbits | (lowbits << 1));
 619         cmd |= (downshift >> 1) | (upshift << 1);
 620         return cmd;
 621 }