src/cpu/intel/model_1067x/model_1067x_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *               2012 secunet Security Networks AG
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <string.h>
  21 #include <cpu/cpu.h>
  22 #include <cpu/x86/mtrr.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <cpu/intel/microcode.h>
  26 #include <cpu/intel/speedstep.h>
  27 #include <cpu/intel/hyperthreading.h>
  28 #include <cpu/x86/cache.h>
  29 #include <cpu/x86/name.h>
  30
  31 #include "chip.h"
  32
  33 static void init_timer(void)
  34 {
  35         /* Set the apic timer to no interrupts and periodic mode */
  36         lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
  37
  38         /* Set the divider to 1, no divider */
  39         lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
  40
  41         /* Set the initial counter to 0xffffffff */
  42         lapic_write(LAPIC_TMICT, 0xffffffff);
  43 }
  44
  45 #define IA32_FEATURE_CONTROL 0x003a
  46
  47 #define CPUID_VMX (1 << 5)
  48 #define CPUID_SMX (1 << 6)
  49 static void enable_vmx(void)
  50 {
  51         struct cpuid_result regs;
  52         msr_t msr;
  53
  54         msr = rdmsr(IA32_FEATURE_CONTROL);
  55
  56         if (msr.lo & (1 << 0)) {
  57                 /* VMX locked. If we set it again we get an illegal
  58                  * instruction
  59                  */
  60                 return;
  61         }
  62
  63         regs = cpuid(1);
  64         if (regs.ecx & CPUID_VMX) {
  65                 msr.lo |= (1 << 2);
  66                 if (regs.ecx & CPUID_SMX)
  67                         msr.lo |= (1 << 1);
  68         }
  69
  70         wrmsr(IA32_FEATURE_CONTROL, msr);
  71
  72         msr.lo |= (1 << 0); /* Set lock bit */
  73
  74         wrmsr(IA32_FEATURE_CONTROL, msr);
  75 }
  76
  77 #define MSR_BBL_CR_CTL3         0x11e
  78
  79 static void configure_c_states(const int quad)
  80 {
  81         msr_t msr;
  82
  83         /* Find pointer to CPU configuration. */
  84         const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
  85         const struct cpu_intel_model_1067x_config *const conf =
  86                 (lapic && lapic->chip_info) ? lapic->chip_info : NULL;
  87
  88         /* Is C5 requested and supported? */
  89         const int c5 = conf && conf->c5 &&
  90                         (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) &&
  91                         !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31));
  92         /* Is C6 requested and supported? */
  93         const int c6 = conf && conf->c6 &&
  94                         ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5;
  95
  96         const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
  97
  98         msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
  99         msr.lo &= ~(1 << 9); // Issue a  single stop grant cycle upon stpclk
 100         msr.lo |=  (1 << 8);
 101         if (quad) {
 102                 msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0);
 103         }
 104         if (c5) {
 105                 msr.lo &= ~(1 << 13);
 106                 msr.lo &= ~(7 <<  0);
 107                 msr.lo |= (1 <<  3); /* Enable dynamic L2. */
 108                 msr.lo |= (1 << 14); /* Enable deeper sleep */
 109         }
 110         /* Next two fields seem to be mutually exclusive: */
 111         msr.lo &= ~(7 << 4);
 112         msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
 113         if (c6)
 114                 msr.lo |= (1 << 25);
 115         wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
 116
 117         /* Set Processor MWAIT IO BASE */
 118         msr.hi = 0;
 119         msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
 120         wrmsr(MSR_PMG_IO_BASE_ADDR, msr);
 121
 122         /* Set IO Capture Address */
 123         msr.hi = 0;
 124         msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16);
 125         wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
 126
 127         if (c5) {
 128                 msr = rdmsr(MSR_BBL_CR_CTL3);
 129                 msr.lo &= ~(7 << 25);
 130                 msr.lo |=  (2 << 25);
 131                 msr.lo &= ~(3 << 30);
 132                 msr.lo |=  (1 << 30);
 133                 wrmsr(MSR_BBL_CR_CTL3, msr);
 134         }
 135 }
 136
 137 static void configure_p_states(const char stepping, const char cores)
 138 {
 139         msr_t msr;
 140
 141         /* Find pointer to CPU configuration. */
 142         const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
 143         struct cpu_intel_model_1067x_config *const conf =
 144                 (lapic && lapic->chip_info) ? lapic->chip_info : NULL;
 145
 146         msr = rdmsr(MSR_EXTENDED_CONFIG);
 147         /* Super LFM supported? */
 148         if (conf && conf->slfm && (msr.lo & (1 << 27)))
 149                 msr.lo |= (1 << 28); /* Enable Super LFM. */
 150         wrmsr(MSR_EXTENDED_CONFIG, msr);
 151
 152         if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) {
 153                                                         /* Turbo supported? */
 154                 if ((stepping == 0xa) && (cores < 4)) {
 155                         msr = rdmsr(MSR_FSB_FREQ);
 156                         msr.lo |= (1 << 3); /* Enable hysteresis. */
 157                         wrmsr(MSR_FSB_FREQ, msr);
 158                 }
 159                 msr = rdmsr(IA32_PERF_CTL);
 160                 msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */
 161                 wrmsr(IA32_PERF_CTL, msr);
 162         }
 163
 164         msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
 165         msr.lo &= ~(1 << 11); /* Enable hw coordination. */
 166         msr.lo |= (1 << 15); /* Lock config until next reset. */
 167         wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
 168 }
 169
 170 #define MSR_EMTTM_CR_TABLE(x)   (0xa8 + (x))
 171 #define MSR_EMTTM_TABLE_NUM     6
 172 static void configure_emttm_tables(void)
 173 {
 174         int i;
 175         int num_states, pstate_idx;
 176         msr_t msr;
 177         sst_table_t pstates;
 178
 179         /* Gather p-state information. */
 180         speedstep_gen_pstates(&pstates);
 181
 182         /* Never turbo mode or Super LFM. */
 183         num_states = pstates.num_states;
 184         if (pstates.states[0].is_turbo)
 185                 --num_states;
 186         if (pstates.states[pstates.num_states - 1].is_slfm)
 187                 --num_states;
 188         /* Repeat lowest p-state if we haven't enough states. */
 189         const int num_lowest_pstate =
 190                 (num_states < MSR_EMTTM_TABLE_NUM)
 191                 ? (MSR_EMTTM_TABLE_NUM - num_states) + 1
 192                 : 1;
 193         /* Start from the lowest entry but skip Super LFM. */
 194         if (pstates.states[pstates.num_states - 1].is_slfm)
 195                 pstate_idx = pstates.num_states - 2;
 196         else
 197                 pstate_idx = pstates.num_states - 1;
 198         for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) {
 199                 if (i >= num_lowest_pstate)
 200                         --pstate_idx;
 201                 const sst_state_t *const pstate = &pstates.states[pstate_idx];
 202                 printk(BIOS_DEBUG, "writing P-State %d: %d, %d, "
 203                                    "%2d, 0x%02x, %d; encoded: 0x%04x\n",
 204                         pstate_idx, pstate->dynfsb, pstate->nonint,
 205                         pstate->ratio, pstate->vid, pstate->power,
 206                         SPEEDSTEP_ENCODE_STATE(*pstate));
 207                 msr.hi = 0;
 208                 msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) &
 209                                                 /* Don't set half ratios. */
 210                                                 ~SPEEDSTEP_RATIO_NONINT;
 211                 wrmsr(MSR_EMTTM_CR_TABLE(i), msr);
 212         }
 213
 214         msr = rdmsr(MSR_EMTTM_CR_TABLE(5));
 215         msr.lo |= (1 << 31); /* lock tables */
 216         wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
 217 }
 218
 219 static void configure_misc(const int eist, const int tm2, const int emttm)
 220 {
 221         msr_t msr;
 222
 223         const u32 sub_cstates = cpuid_edx(5);
 224
 225         msr = rdmsr(IA32_MISC_ENABLES);
 226         msr.lo |= (1 << 3);     /* TM1 enable */
 227         if (tm2)
 228                 msr.lo |= (1 << 13);    /* TM2 enable */
 229         msr.lo |= (1 << 17);    /* Bidirectional PROCHOT# */
 230         msr.lo |= (1 << 18);    /* MONITOR/MWAIT enable */
 231
 232         msr.lo |= (1 << 10);    /* FERR# multiplexing */
 233
 234         if (eist)
 235                 msr.lo |= (1 << 16);    /* Enhanced SpeedStep Enable */
 236
 237         /* Enable C2E */
 238         if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) {
 239                 msr.lo |= (1 << 26);
 240         }
 241
 242         /* Enable C4E */
 243         if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) {
 244                 msr.hi |= (1 << (32 - 32)); // C4E
 245                 msr.hi |= (1 << (33 - 32)); // Hard C4E
 246         }
 247
 248         /* Enable EMTTM */
 249         if (emttm)
 250                 msr.hi |= (1 << (36 - 32));
 251
 252         /* Enable turbo mode */
 253         if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))
 254                 msr.hi &= ~(1 << (38 - 32));
 255
 256         wrmsr(IA32_MISC_ENABLES, msr);
 257
 258         if (eist) {
 259                 msr.lo |= (1 << 20);    /* Lock Enhanced SpeedStep Enable */
 260                 wrmsr(IA32_MISC_ENABLES, msr);
 261         }
 262 }
 263
 264 #define PIC_SENS_CFG    0x1aa
 265 static void configure_pic_thermal_sensors(const int tm2, const int quad)
 266 {
 267         msr_t msr;
 268
 269         msr = rdmsr(PIC_SENS_CFG);
 270
 271         if (quad)
 272                 msr.lo |=  (1 << 31);
 273         else
 274                 msr.lo &= ~(1 << 31);
 275         if (tm2)
 276                 msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */
 277         msr.lo |= (1 << 21); // inter-core lock TM1
 278         msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */
 279
 280         wrmsr(PIC_SENS_CFG, msr);
 281 }
 282
 283 static void model_1067x_init(struct device *cpu)
 284 {
 285         char processor_name[49];
 286
 287
 288         /* Gather some information: */
 289
 290         const struct cpuid_result cpuid1 = cpuid(1);
 291
 292         /* Read stepping. */
 293         const char stepping = cpuid1.eax & 0xf;
 294         /* Read number of cores. */
 295         const char cores = (cpuid1.ebx >> 16) & 0xf;
 296         /* Is this a quad core? */
 297         const char quad = cores > 2;
 298         /* Is this even a multiprocessor? */
 299         const char mp = cores > 1;
 300
 301         /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */
 302         const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4);
 303
 304         /* Is enhanced speedstep supported? */
 305         const char eist = (cpuid1.ecx & (1 << 7)) &&
 306                           !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17));
 307         /* Test for TM2 only if EIST is available. */
 308         const char tm2 = eist && (cpuid1.ecx & (1 << 8));
 309
 310
 311         /* Turn on caching if we haven't already */
 312         x86_enable_cache();
 313
 314         /* Update the microcode */
 315         intel_update_microcode_from_cbfs();
 316
 317         /* Print processor name */
 318         fill_processor_name(processor_name);
 319         printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 320
 321         /* Setup MTRRs */
 322         x86_setup_mtrrs();
 323         x86_mtrr_check();
 324
 325         /* Enable the local cpu apics */
 326         setup_lapic();
 327
 328         /* Initialize the APIC timer */
 329         init_timer();
 330
 331         /* Enable virtualization */
 332         enable_vmx();
 333
 334         /* Configure C States */
 335         configure_c_states(quad);
 336
 337         /* Configure P States */
 338         configure_p_states(stepping, cores);
 339
 340         /* EMTTM */
 341         if (emttm)
 342                 configure_emttm_tables();
 343
 344         /* Configure Enhanced SpeedStep and Thermal Sensors */
 345         configure_misc(eist, tm2, emttm);
 346
 347         /* PIC thermal sensor control */
 348         configure_pic_thermal_sensors(tm2, quad);
 349
 350         /* Start up my cpu siblings */
 351         intel_sibling_init(cpu);
 352 }
 353
 354 static struct device_operations cpu_dev_ops = {
 355         .init     = model_1067x_init,
 356 };
 357
 358 static struct cpu_device_id cpu_table[] = {
 359         { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */
 360         { X86_VENDOR_INTEL, 0x10677 },
 361         { X86_VENDOR_INTEL, 0x1067A },
 362         { 0, 0 },
 363 };
 364
 365 static const struct cpu_driver driver __cpu_driver = {
 366         .ops      = &cpu_dev_ops,
 367         .id_table = cpu_table,
 368 };
 369
 370 struct chip_operations cpu_intel_model_1067x_ops = {
 371         CHIP_NAME("Intel Penryn CPU")
 372 };