src/cpu/intel/fsp_model_206ax/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 coresystems GmbH
   5  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <types.h>
  19 #include <console/console.h>
  20 #include <arch/acpi.h>
  21 #include <arch/acpigen.h>
  22 #include <arch/cpu.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/intel/speedstep.h>
  25 #include <cpu/intel/turbo.h>
  26 #include <device/device.h>
  27 #include "model_206ax.h"
  28 #include "chip.h"
  29
  30 static int get_cores_per_package(void)
  31 {
  32         struct cpuinfo_x86 c;
  33         struct cpuid_result result;
  34         int cores = 1;
  35
  36         get_fms(&c, cpuid_eax(1));
  37         if (c.x86 != 6)
  38                 return 1;
  39
  40         result = cpuid_ext(0xb, 1);
  41         cores = result.ebx & 0xff;
  42
  43         return cores;
  44 }
  45
  46 static void generate_cstate_entries(acpi_cstate_t *cstates,
  47                                    int c1, int c2, int c3)
  48 {
  49         int cstate_count = 0;
  50
  51         /* Count number of active C-states */
  52         if (c1 > 0)
  53                 ++cstate_count;
  54         if (c2 > 0)
  55                 ++cstate_count;
  56         if (c3 > 0)
  57                 ++cstate_count;
  58         if (!cstate_count)
  59                 return;
  60
  61         acpigen_write_package(cstate_count + 1);
  62         acpigen_write_byte(cstate_count);
  63
  64         /* Add an entry if the level is enabled */
  65         if (c1 > 0) {
  66                 cstates[c1].ctype = 1;
  67                 acpigen_write_CST_package_entry(&cstates[c1]);
  68         }
  69         if (c2 > 0) {
  70                 cstates[c2].ctype = 2;
  71                 acpigen_write_CST_package_entry(&cstates[c2]);
  72         }
  73         if (c3 > 0) {
  74                 cstates[c3].ctype = 3;
  75                 acpigen_write_CST_package_entry(&cstates[c3]);
  76         }
  77
  78         acpigen_pop_len();
  79 }
  80
  81 static void generate_C_state_entries(void)
  82 {
  83         struct cpu_info *info;
  84         struct cpu_driver *cpu;
  85         struct device *lapic;
  86         struct cpu_intel_fsp_model_206ax_config *conf = NULL;
  87
  88         /* Find the SpeedStep CPU in the device tree using magic APIC ID */
  89         lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
  90         if (!lapic)
  91                 return;
  92         conf = lapic->chip_info;
  93         if (!conf)
  94                 return;
  95
  96         /* Find CPU map of supported C-states */
  97         info = cpu_info();
  98         if (!info)
  99                 return;
 100         cpu = find_cpu_driver(info->cpu);
 101         if (!cpu || !cpu->cstates)
 102                 return;
 103
 104         acpigen_write_method("_CST", 0);
 105
 106         /* If running on AC power */
 107         acpigen_emit_byte(0xa0);                /* IfOp */
 108         acpigen_write_len_f();          /* PkgLength */
 109         acpigen_emit_namestring("PWRS");
 110         acpigen_emit_byte(0xa4);        /* ReturnOp */
 111         generate_cstate_entries(cpu->cstates, conf->c1_acpower,
 112                                          conf->c2_acpower, conf->c3_acpower);
 113         acpigen_pop_len();
 114
 115         /* Else on battery power */
 116         acpigen_emit_byte(0xa4);        /* ReturnOp */
 117         generate_cstate_entries(cpu->cstates, conf->c1_battery,
 118                                         conf->c2_battery, conf->c3_battery);
 119         acpigen_pop_len();
 120 }
 121
 122 static acpi_tstate_t tss_table_fine[] = {
 123         { 100, 1000, 0, 0x00, 0 },
 124         { 94, 940, 0, 0x1f, 0 },
 125         { 88, 880, 0, 0x1e, 0 },
 126         { 82, 820, 0, 0x1d, 0 },
 127         { 75, 760, 0, 0x1c, 0 },
 128         { 69, 700, 0, 0x1b, 0 },
 129         { 63, 640, 0, 0x1a, 0 },
 130         { 57, 580, 0, 0x19, 0 },
 131         { 50, 520, 0, 0x18, 0 },
 132         { 44, 460, 0, 0x17, 0 },
 133         { 38, 400, 0, 0x16, 0 },
 134         { 32, 340, 0, 0x15, 0 },
 135         { 25, 280, 0, 0x14, 0 },
 136         { 19, 220, 0, 0x13, 0 },
 137         { 13, 160, 0, 0x12, 0 },
 138 };
 139
 140 static acpi_tstate_t tss_table_coarse[] = {
 141         { 100, 1000, 0, 0x00, 0 },
 142         { 88, 875, 0, 0x1f, 0 },
 143         { 75, 750, 0, 0x1e, 0 },
 144         { 63, 625, 0, 0x1d, 0 },
 145         { 50, 500, 0, 0x1c, 0 },
 146         { 38, 375, 0, 0x1b, 0 },
 147         { 25, 250, 0, 0x1a, 0 },
 148         { 13, 125, 0, 0x19, 0 },
 149 };
 150
 151 static void generate_T_state_entries(int core, int cores_per_package)
 152 {
 153         /* Indicate SW_ALL coordination for T-states */
 154         acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
 155
 156         /* Indicate FFixedHW so OS will use MSR */
 157         acpigen_write_empty_PTC();
 158
 159         /* Set a T-state limit that can be modified in NVS */
 160         acpigen_write_TPC("\\TLVL");
 161
 162         /*
 163          * CPUID.(EAX=6):EAX[5] indicates support
 164          * for extended throttle levels.
 165          */
 166         if (cpuid_eax(6) & (1 << 5))
 167                 acpigen_write_TSS_package(
 168                         ARRAY_SIZE(tss_table_fine), tss_table_fine);
 169         else
 170                 acpigen_write_TSS_package(
 171                         ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 172 }
 173
 174 static int calculate_power(int tdp, int p1_ratio, int ratio)
 175 {
 176         u32 m;
 177         u32 power;
 178
 179         /*
 180          * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
 181          *
 182          * Power = (ratio / p1_ratio) * m * tdp
 183          */
 184
 185         m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 186         m = (m * m) / 1000;
 187
 188         power = ((ratio * 100000 / p1_ratio) / 100);
 189         power *= (m / 100) * (tdp / 1000);
 190         power /= 1000;
 191
 192         return (int)power;
 193 }
 194
 195 static void generate_P_state_entries(int core, int cores_per_package)
 196 {
 197         int ratio_min, ratio_max, ratio_turbo, ratio_step;
 198         int coord_type, power_max, power_unit, num_entries;
 199         int ratio, power, clock, clock_max;
 200         msr_t msr;
 201
 202         /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
 203         msr = rdmsr(MSR_MISC_PWR_MGMT);
 204         if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
 205                 coord_type = SW_ANY;
 206         else
 207                 coord_type = HW_ALL;
 208
 209         /* Get bus ratio limits and calculate clock speeds */
 210         msr = rdmsr(MSR_PLATFORM_INFO);
 211         ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
 212
 213         /* Determine if this CPU has configurable TDP */
 214         if (cpu_config_tdp_levels()) {
 215                 /* Set max ratio to nominal TDP ratio */
 216                 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
 217                 ratio_max = msr.lo & 0xff;
 218         } else {
 219                 /* Max Non-Turbo Ratio */
 220                 ratio_max = (msr.lo >> 8) & 0xff;
 221         }
 222         clock_max = ratio_max * SANDYBRIDGE_BCLK;
 223
 224         /* Calculate CPU TDP in mW */
 225         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 226         power_unit = 2 << ((msr.lo & 0xf) - 1);
 227         msr = rdmsr(MSR_PKG_POWER_SKU);
 228         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 229
 230         /* Write _PCT indicating use of FFixedHW */
 231         acpigen_write_empty_PCT();
 232
 233         /* Write _PPC with no limit on supported P-state */
 234         acpigen_write_PPC_NVS();
 235
 236         /* Write PSD indicating configured coordination type */
 237         acpigen_write_PSD_package(core, cores_per_package, coord_type);
 238
 239         /* Add P-state entries in _PSS table */
 240         acpigen_write_name("_PSS");
 241
 242         /* Determine ratio points */
 243         ratio_step = PSS_RATIO_STEP;
 244         num_entries = (ratio_max - ratio_min) / ratio_step;
 245         while (num_entries > PSS_MAX_ENTRIES-1) {
 246                 ratio_step <<= 1;
 247                 num_entries >>= 1;
 248         }
 249
 250         /* P[T] is Turbo state if enabled */
 251         if (get_turbo_state() == TURBO_ENABLED) {
 252                 /* _PSS package count including Turbo */
 253                 acpigen_write_package(num_entries + 2);
 254
 255                 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 256                 ratio_turbo = msr.lo & 0xff;
 257
 258                 /* Add entry for Turbo ratio */
 259                 acpigen_write_PSS_package(
 260                         clock_max + 1,          /*MHz*/
 261                         power_max,              /*mW*/
 262                         PSS_LATENCY_TRANSITION, /*lat1*/
 263                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 264                         ratio_turbo << 8,       /*control*/
 265                         ratio_turbo << 8);      /*status*/
 266         } else {
 267                 /* _PSS package count without Turbo */
 268                 acpigen_write_package(num_entries + 1);
 269         }
 270
 271         /* First regular entry is max non-turbo ratio */
 272         acpigen_write_PSS_package(
 273                 clock_max,              /*MHz*/
 274                 power_max,              /*mW*/
 275                 PSS_LATENCY_TRANSITION, /*lat1*/
 276                 PSS_LATENCY_BUSMASTER,  /*lat2*/
 277                 ratio_max << 8,         /*control*/
 278                 ratio_max << 8);        /*status*/
 279
 280         /* Generate the remaining entries */
 281         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 282              ratio >= ratio_min; ratio -= ratio_step) {
 283
 284                 /* Calculate power at this ratio */
 285                 power = calculate_power(power_max, ratio_max, ratio);
 286                 clock = ratio * SANDYBRIDGE_BCLK;
 287
 288                 acpigen_write_PSS_package(
 289                         clock,                  /*MHz*/
 290                         power,                  /*mW*/
 291                         PSS_LATENCY_TRANSITION, /*lat1*/
 292                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 293                         ratio << 8,             /*control*/
 294                         ratio << 8);            /*status*/
 295         }
 296
 297         /* Fix package length */
 298         acpigen_pop_len();
 299 }
 300
 301 void generate_cpu_entries(device_t device)
 302 {
 303         int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 304         int totalcores = dev_count_cpu();
 305         int cores_per_package = get_cores_per_package();
 306         int numcpus = totalcores/cores_per_package;
 307
 308         printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
 309                numcpus, cores_per_package);
 310
 311         for (cpuID = 1; cpuID <= numcpus; cpuID++) {
 312                 for (coreID=1; coreID<=cores_per_package; coreID++) {
 313                         if (coreID>1) {
 314                                 pcontrol_blk = 0;
 315                                 plen = 0;
 316                         }
 317
 318                         /* Generate processor \_PR.CPUx */
 319                         acpigen_write_processor(
 320                                 (cpuID-1)*cores_per_package+coreID-1,
 321                                 pcontrol_blk, plen);
 322
 323                         /* Generate P-state tables */
 324                         generate_P_state_entries(
 325                                 cpuID-1, cores_per_package);
 326
 327                         /* Generate C-state tables */
 328                         generate_C_state_entries();
 329
 330                         /* Generate T-state tables */
 331                         generate_T_state_entries(
 332                                 cpuID-1, cores_per_package);
 333
 334                         acpigen_pop_len();
 335                 }
 336         }
 337 }
 338
 339 struct chip_operations cpu_intel_model_206ax_ops = {
 340         CHIP_NAME("Intel SandyBridge/IvyBridge CPU")
 341 };