src/cpu/amd/model_10xxx/model_10xxx_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <cpu/x86/msr.h>
  19 #include <cpu/amd/mtrr.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <string.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/x86/smm.h>
  25 #include <cpu/x86/pae.h>
  26 #include <pc80/mc146818rtc.h>
  27 #include <cpu/x86/lapic.h>
  28 #include "northbridge/amd/amdfam10/amdfam10.h"
  29 #include <cpu/amd/model_10xxx_rev.h>
  30 #include <cpu/cpu.h>
  31 #include <cpu/x86/cache.h>
  32 #include <cpu/x86/mtrr.h>
  33 #include <cpu/amd/multicore.h>
  34 #include <cpu/amd/model_10xxx_msr.h>
  35
  36 #define MCI_STATUS 0x401
  37
  38 static void model_10xxx_init(device_t dev)
  39 {
  40         u8 i;
  41         msr_t msr;
  42         struct node_core_id id;
  43 #if CONFIG_LOGICAL_CPUS
  44         u32 siblings;
  45 #endif
  46
  47         id = get_node_core_id(read_nb_cfg_54());        /* nb_cfg_54 can not be set */
  48         printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
  49
  50         /* Turn on caching if we haven't already */
  51         x86_enable_cache();
  52         amd_setup_mtrrs();
  53         x86_mtrr_check();
  54
  55         disable_cache();
  56
  57         /* zero the machine check error status registers */
  58         msr.lo = 0;
  59         msr.hi = 0;
  60         for (i = 0; i < 5; i++) {
  61                 wrmsr(MCI_STATUS + (i * 4), msr);
  62         }
  63
  64         enable_cache();
  65
  66         /* Enable the local cpu apics */
  67         setup_lapic();
  68
  69         /* Set the processor name string */
  70         init_processor_name();
  71
  72 #if CONFIG_LOGICAL_CPUS
  73         siblings = cpuid_ecx(0x80000008) & 0xff;
  74
  75         if (siblings > 0) {
  76                 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
  77                 msr.lo |= 1 << 28;
  78                 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
  79
  80                 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
  81                 msr.hi |= 1 << (33 - 32);
  82                 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
  83         }
  84         printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
  85 #endif
  86
  87         /* DisableCf8ExtCfg */
  88         msr = rdmsr(NB_CFG_MSR);
  89         msr.hi &= ~(1 << (46 - 32));
  90         wrmsr(NB_CFG_MSR, msr);
  91
  92         msr = rdmsr(BU_CFG2_MSR);
  93         /* Clear ClLinesToNbDis */
  94         msr.lo &= ~(1 << 15);
  95         /* Clear bit 35 as per Erratum 343 */
  96         msr.hi &= ~(1 << (35-32));
  97         wrmsr(BU_CFG2_MSR, msr);
  98
  99         if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
 100                 printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
 101
 102                 /* Set SMM base address for this CPU */
 103                 msr = rdmsr(SMM_BASE_MSR);
 104                 msr.lo = SMM_BASE - (lapicid() * 0x400);
 105                 wrmsr(SMM_BASE_MSR, msr);
 106
 107                 /* Enable the SMM memory window */
 108                 msr = rdmsr(SMM_MASK_MSR);
 109                 msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
 110                 wrmsr(SMM_MASK_MSR, msr);
 111         } else {
 112                 printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
 113
 114                 /* Set SMM base address for this CPU */
 115                 msr = rdmsr(SMM_BASE_MSR);
 116                 msr.lo = SMM_BASE - (lapicid() * 0x400);
 117                 wrmsr(SMM_BASE_MSR, msr);
 118
 119                 /* Disable the SMM memory window */
 120                 msr.hi = 0x0;
 121                 msr.lo = 0x0;
 122                 wrmsr(SMM_MASK_MSR, msr);
 123         }
 124
 125         /* Set SMMLOCK to avoid exploits messing with SMM */
 126         msr = rdmsr(HWCR_MSR);
 127         msr.lo |= (1 << 0);
 128         wrmsr(HWCR_MSR, msr);
 129
 130 }
 131
 132 static struct device_operations cpu_dev_ops = {
 133         .init = model_10xxx_init,
 134 };
 135
 136 static struct cpu_device_id cpu_table[] = {
 137 //AMD_GH_SUPPORT
 138         { X86_VENDOR_AMD, 0x100f00 },           /* SH-F0 L1 */
 139         { X86_VENDOR_AMD, 0x100f10 },           /* M2 */
 140         { X86_VENDOR_AMD, 0x100f20 },           /* S1g1 */
 141         { X86_VENDOR_AMD, 0x100f21 },
 142         { X86_VENDOR_AMD, 0x100f2A },
 143         { X86_VENDOR_AMD, 0x100f22 },
 144         { X86_VENDOR_AMD, 0x100f23 },
 145         { X86_VENDOR_AMD, 0x100f40 },           /* RB-C0 */
 146         { X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */
 147         { X86_VENDOR_AMD, 0x100F43 },           /* RB-C3 */
 148         { X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */
 149         { X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
 150         { X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
 151         { X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
 152         { X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
 153         { X86_VENDOR_AMD, 0x100F91 },           /* HY-D1 */
 154         { X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
 155         { 0, 0 },
 156 };
 157
 158 static const struct cpu_driver model_10xxx __cpu_driver = {
 159         .ops      = &cpu_dev_ops,
 160         .id_table = cpu_table,
 161 };