src/cpu/amd/agesa/family15tn/fixme.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <cpu/x86/mtrr.h>
  17 #include <northbridge/amd/agesa/agesawrapper.h>
  18 #include "amdlib.h"
  19
  20 void amd_initcpuio(void)
  21 {
  22         UINT64                        MsrReg;
  23         UINT32                        PciData;
  24         PCI_ADDR                      PciAddress;
  25         AMD_CONFIG_PARAMS             StdHeader;
  26
  27         /* Enable legacy video routing: D18F1xF4 VGA Enable */
  28         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
  29         PciData = 1;
  30         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  31
  32         /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
  33          * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
  34          * set to non-posted regions.
  35          */
  36         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
  37         PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
  38         PciData |= 1 << 7;    /* set NP (non-posted) bit */
  39         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  40         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
  41         PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
  42         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  43
  44         /* Map the remaining PCI hole as posted MMIO */
  45         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
  46         PciData = 0x00FECF00; /* last address before non-posted range */
  47         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  48         LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
  49         MsrReg = (MsrReg >> 8) | 3;
  50         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
  51         PciData = (UINT32)MsrReg;
  52         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  53
  54         /* Send all IO (0000-FFFF) to southbridge. */
  55         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
  56         PciData = 0x0000F000;
  57         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  58         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
  59         PciData = 0x00000003;
  60         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  61 }
  62
  63 void amd_initmmio(void)
  64 {
  65         UINT64                        MsrReg;
  66         AMD_CONFIG_PARAMS             StdHeader;
  67
  68         /*
  69           Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
  70           Address MSR register.
  71         */
  72         MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
  73         LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
  74
  75         /*
  76           Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
  77         */
  78         LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
  79         MsrReg = MsrReg | 0x0000400000000000;
  80         LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
  81
  82         /* Set ROM cache onto WP to decrease post time */
  83         MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
  84         LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
  85         MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
  86         LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
  87 }