util/inteltool/spi.c

   1
   2 #include <stdio.h>
   3 #include <stdlib.h>
   4 #include "inteltool.h"
   5
   6 static const io_register_t pch_bios_cntl_registers[] = {
   7         { 0x0, 1, "BIOSWE - write enable" },
   8         { 0x1, 1, "BLE - lock enable" },
   9         { 0x2, 2, "SPI Read configuration" },
  10         { 0x4, 1, "TopSwapStatus" },
  11         { 0x5, 1, "SMM Bios Write Protect Disable" },
  12         { 0x6, 2, "reserved" },
  13 };
  14
  15 #define ICH9_SPIBAR 0x3800
  16 #define ICH78_SPIBAR 0x3020
  17
  18 static const io_register_t spi_bar_registers[] = {
  19         { 0x00, 4, "BFPR - BIOS Flash primary region" },
  20         { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
  21         { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
  22         { 0x08, 4, "FADDR - Flash Address" },
  23         { 0x0c, 4, "Reserved" },
  24         { 0x10, 4, "FDATA0" },
  25         /* 0x10 .. 0x4f are filled with data */
  26         { 0x50, 4, "FRACC - Flash Region Access Permissions" },
  27         { 0x54, 4, "Flash Region 0" },
  28         { 0x58, 4, "Flash Region 1" },
  29         { 0x5c, 4, "Flash Region 2" },
  30         { 0x60, 4, "Flash Region 3" },
  31         { 0x64, 4, "Flash Region 4" },
  32         { 0x74, 4, "FPR0 Flash Protected Range 0" },
  33         { 0x78, 4, "FPR0 Flash Protected Range 1" },
  34         { 0x7c, 4, "FPR0 Flash Protected Range 2" },
  35         { 0x80, 4, "FPR0 Flash Protected Range 3" },
  36         { 0x84, 4, "FPR0 Flash Protected Range 4" },
  37         { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
  38         { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
  39         { 0x94, 2, "PREOP - Prefix opcode Configuration" },
  40         { 0x96, 2, "OPTYPE - Opcode Type Configuration" },
  41         { 0x98, 8, "OPMENU - Opcode Menu Configuration" },
  42         { 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
  43         { 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
  44         { 0xb8, 4, "Reserved" },
  45         { 0xc0, 4, "AFC - Additional Flash Control" },
  46         { 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
  47         { 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
  48         { 0xd0, 4, "FPB - Flash Partition Boundary" },
  49 };
  50
  51 static const io_register_t ich7_spi_bar_registers[] = {
  52         { 0x00, 2, "SPIS - SPI Status" },
  53         { 0x02, 2, "SPIC - SPI Control" },
  54         { 0x04, 4, "SPIA - SPI Address" },
  55         /*
  56          *0x08 .. 0x47 are filled with data
  57          *0x48 .. 0x4f is not mentioned by datasheet
  58          */
  59         { 0x50, 4, "BBAR - BIOS Base Address Configuration" },
  60         { 0x54, 2, "PREOP Prefix Opcode Configuration" },
  61         { 0x56, 2, "OPTYPE Opcode Type Configuration" },
  62         { 0x58, 8, "OPMENU Opcode Menu Configuration" },
  63         { 0x60, 4, "PBR0 Protected BIOS Range 0" },
  64         { 0x64, 4, "PBR1 Protected BIOS Range 1" },
  65         { 0x68, 4, "PBR2 Protected BIOS Range 2" },
  66 };
  67
  68 int print_bioscntl(struct pci_dev *sb)
  69 {
  70         int i, size = 0;
  71         unsigned char bios_cntl = 0xff;
  72         const io_register_t *bios_cntl_register = NULL;
  73
  74         printf("\n============= SPI / BIOS CNTL =============\n\n");
  75
  76         switch (sb->device_id) {
  77         case PCI_DEVICE_ID_INTEL_3400:
  78         case PCI_DEVICE_ID_INTEL_3420:
  79         case PCI_DEVICE_ID_INTEL_3450:
  80         case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
  81         case PCI_DEVICE_ID_INTEL_B55_A:
  82         case PCI_DEVICE_ID_INTEL_B55_B:
  83         case PCI_DEVICE_ID_INTEL_H55:
  84         case PCI_DEVICE_ID_INTEL_H57:
  85         case PCI_DEVICE_ID_INTEL_P55:
  86         case PCI_DEVICE_ID_INTEL_Q57:
  87         case PCI_DEVICE_ID_INTEL_3400_MOBILE:
  88         case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
  89         case PCI_DEVICE_ID_INTEL_HM55:
  90         case PCI_DEVICE_ID_INTEL_HM57:
  91         case PCI_DEVICE_ID_INTEL_PM55:
  92         case PCI_DEVICE_ID_INTEL_QM57:
  93         case PCI_DEVICE_ID_INTEL_QS57:
  94                 bios_cntl = pci_read_byte(sb, 0xdc);
  95                 bios_cntl_register = pch_bios_cntl_registers;
  96                 size = ARRAY_SIZE(pch_bios_cntl_registers);
  97                 break;
  98         default:
  99                 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
 100                 return 1;
 101         }
 102
 103         printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
 104
 105         if (bios_cntl_register) {
 106                 for (i = 0; i < size; i++) {
 107                         unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
 108                         val &= ((1 << bios_cntl_register[i].size) -1);
 109                         printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
 110                 }
 111         }
 112
 113         return 0;
 114 }
 115
 116 int print_spibar(struct pci_dev *sb) {
 117         int i, size = 0, rcba_size = 0x4000;
 118         volatile uint8_t *rcba;
 119         uint32_t rcba_phys;
 120         const io_register_t *spi_register = NULL;
 121         uint32_t spibaroffset;
 122
 123         printf("\n============= SPI Bar ==============\n\n");
 124
 125         switch (sb->device_id) {
 126         case PCI_DEVICE_ID_INTEL_ICH6:
 127                 printf("This southbridge does not have a SPI controller.\n");
 128                 return 1;
 129         case PCI_DEVICE_ID_INTEL_ICH7:
 130         case PCI_DEVICE_ID_INTEL_ICH7M:
 131         case PCI_DEVICE_ID_INTEL_ICH7DH:
 132         case PCI_DEVICE_ID_INTEL_ICH7MDH:
 133                 spibaroffset = ICH78_SPIBAR;
 134                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 135                 size = ARRAY_SIZE(ich7_spi_bar_registers);
 136                 spi_register = ich7_spi_bar_registers;
 137                 break;
 138         case PCI_DEVICE_ID_INTEL_ICH8:
 139                 spibaroffset = ICH78_SPIBAR;
 140                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 141                 size = ARRAY_SIZE(spi_bar_registers);
 142                 spi_register = spi_bar_registers;
 143                 break;
 144         case PCI_DEVICE_ID_INTEL_ICH8M:
 145         case PCI_DEVICE_ID_INTEL_ICH8ME:
 146         case PCI_DEVICE_ID_INTEL_ICH9DH:
 147         case PCI_DEVICE_ID_INTEL_ICH9DO:
 148         case PCI_DEVICE_ID_INTEL_ICH9R:
 149         case PCI_DEVICE_ID_INTEL_ICH9:
 150         case PCI_DEVICE_ID_INTEL_ICH9M:
 151         case PCI_DEVICE_ID_INTEL_ICH9ME:
 152         case PCI_DEVICE_ID_INTEL_ICH10R:
 153         case PCI_DEVICE_ID_INTEL_NM10:
 154         case PCI_DEVICE_ID_INTEL_I63XX:
 155         case PCI_DEVICE_ID_INTEL_3400:
 156         case PCI_DEVICE_ID_INTEL_3420:
 157         case PCI_DEVICE_ID_INTEL_3450:
 158         case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
 159         case PCI_DEVICE_ID_INTEL_3400_MOBILE:
 160         case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
 161         case PCI_DEVICE_ID_INTEL_B55_A:
 162         case PCI_DEVICE_ID_INTEL_B55_B:
 163         case PCI_DEVICE_ID_INTEL_H55:
 164         case PCI_DEVICE_ID_INTEL_H57:
 165         case PCI_DEVICE_ID_INTEL_HM55:
 166         case PCI_DEVICE_ID_INTEL_HM57:
 167         case PCI_DEVICE_ID_INTEL_P55:
 168         case PCI_DEVICE_ID_INTEL_PM55:
 169         case PCI_DEVICE_ID_INTEL_Q57:
 170         case PCI_DEVICE_ID_INTEL_QM57:
 171         case PCI_DEVICE_ID_INTEL_QS57:
 172         case PCI_DEVICE_ID_INTEL_Z68:
 173         case PCI_DEVICE_ID_INTEL_P67:
 174         case PCI_DEVICE_ID_INTEL_UM67:
 175         case PCI_DEVICE_ID_INTEL_HM65:
 176         case PCI_DEVICE_ID_INTEL_H67:
 177         case PCI_DEVICE_ID_INTEL_HM67:
 178         case PCI_DEVICE_ID_INTEL_Q65:
 179         case PCI_DEVICE_ID_INTEL_QS67:
 180         case PCI_DEVICE_ID_INTEL_Q67:
 181         case PCI_DEVICE_ID_INTEL_QM67:
 182         case PCI_DEVICE_ID_INTEL_B65:
 183         case PCI_DEVICE_ID_INTEL_C202:
 184         case PCI_DEVICE_ID_INTEL_C204:
 185         case PCI_DEVICE_ID_INTEL_C206:
 186         case PCI_DEVICE_ID_INTEL_H61:
 187         case PCI_DEVICE_ID_INTEL_Z77:
 188         case PCI_DEVICE_ID_INTEL_Z75:
 189         case PCI_DEVICE_ID_INTEL_Q77:
 190         case PCI_DEVICE_ID_INTEL_Q75:
 191         case PCI_DEVICE_ID_INTEL_B75:
 192         case PCI_DEVICE_ID_INTEL_H77:
 193         case PCI_DEVICE_ID_INTEL_C216:
 194         case PCI_DEVICE_ID_INTEL_QM77:
 195         case PCI_DEVICE_ID_INTEL_QS77:
 196         case PCI_DEVICE_ID_INTEL_HM77:
 197         case PCI_DEVICE_ID_INTEL_UM77:
 198         case PCI_DEVICE_ID_INTEL_HM76:
 199         case PCI_DEVICE_ID_INTEL_HM75:
 200         case PCI_DEVICE_ID_INTEL_HM70:
 201         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
 202         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
 203         case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
 204         case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
 205                 spibaroffset = ICH9_SPIBAR;
 206                 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
 207                 size = ARRAY_SIZE(spi_bar_registers);
 208                 spi_register = spi_bar_registers;
 209                 break;
 210         case PCI_DEVICE_ID_INTEL_ICH:
 211         case PCI_DEVICE_ID_INTEL_ICH0:
 212         case PCI_DEVICE_ID_INTEL_ICH2:
 213         case PCI_DEVICE_ID_INTEL_ICH4:
 214         case PCI_DEVICE_ID_INTEL_ICH4M:
 215         case PCI_DEVICE_ID_INTEL_ICH5:
 216                 printf("This southbridge does not have RCBA.\n");
 217                 return 1;
 218         default:
 219                 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
 220                 return 1;
 221         }
 222
 223         rcba = map_physical(rcba_phys, rcba_size);
 224         if (rcba == NULL) {
 225                 perror("Error mapping RCBA");
 226                 exit(1);
 227         }
 228
 229         for (i = 0; i < size; i++) {
 230                 switch(spi_register[i].size) {
 231                         case 1:
 232                                 printf("0x%08x = %s\n", *(uint8_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 233                                 break;
 234                         case 2:
 235                                 printf("0x%08x = %s\n", *(uint16_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 236                                 break;
 237                         case 4:
 238                                 printf("0x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
 239                                 break;
 240                         case 8:
 241                                 printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name);
 242                                 break;
 243                 }
 244         }
 245
 246         unmap_physical((void *)rcba, rcba_size);
 247         return 0;
 248 }
 249
 250 int print_spi(struct pci_dev *sb) {
 251         return (print_bioscntl(sb) || print_spibar(sb));
 252 }