1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <drivers/i2c/designware/dw_i2c.h>
7 #include <intelblocks/cfg.h>
8 #include <intelblocks/gpio.h>
9 #include <intelblocks/gspi.h>
10 #include <intelblocks/power_limit.h>
13 #include <soc/pci_devs.h>
15 #include <soc/serialio.h>
19 #define MAX_HD_AUDIO_DMIC_LINKS 2
20 #define MAX_HD_AUDIO_SNDW_LINKS 4
21 #define MAX_HD_AUDIO_SSP_LINKS 6
23 struct soc_intel_jasperlake_config
{
25 /* Common struct containing soc config data required by common code */
26 struct soc_intel_common_config common_soc_config
;
28 /* Common struct containing power limits configuration information */
29 struct soc_power_limits_config power_limits_config
;
31 /* Gpio group routed to each dword of the GPE0 block. Values are
32 * of the form PMC_GPP_[A:U] or GPD. */
33 uint8_t pmc_gpe0_dw0
; /* GPE0_31_0 STS/EN */
34 uint8_t pmc_gpe0_dw1
; /* GPE0_63_32 STS/EN */
35 uint8_t pmc_gpe0_dw2
; /* GPE0_95_64 STS/EN */
37 /* Generic IO decode ranges */
43 /* Enable S0iX support */
45 /* Enable DPTF support */
48 /* Deep SX enable for both AC and DC */
49 int deep_s3_enable_ac
;
50 int deep_s3_enable_dc
;
51 int deep_s5_enable_ac
;
52 int deep_s5_enable_dc
;
54 /* Deep Sx Configuration
55 * DSX_EN_WAKE_PIN - Enable WAKE# pin
56 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
57 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
58 uint32_t deep_sx_config
;
60 /* TCC activation offset */
63 /* System Agent dynamic frequency support.
64 * When enabled memory will be training at different frequencies.
65 * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2
66 * (high), 4:Enabled */
75 /* Rank Margin Tool. 1:Enable, 0:Disable */
79 struct usb2_port_config usb2_ports
[16];
80 struct usb3_port_config usb3_ports
[10];
81 /* Wake Enable Bitmap for USB2 ports */
82 uint16_t usb2_wake_enable_bitmap
;
83 /* Wake Enable Bitmap for USB3 ports */
84 uint16_t usb3_wake_enable_bitmap
;
88 uint8_t SataSalpSupport
;
89 uint8_t SataPortsEnable
[8];
90 uint8_t SataPortsDevSlp
[8];
93 uint8_t PchHdaDspEnable
;
94 uint8_t PchHdaAudioLinkHdaEnable
;
95 uint8_t PchHdaAudioLinkDmicEnable
[MAX_HD_AUDIO_DMIC_LINKS
];
96 uint8_t PchHdaAudioLinkSspEnable
[MAX_HD_AUDIO_SSP_LINKS
];
97 uint8_t PchHdaAudioLinkSndwEnable
[MAX_HD_AUDIO_SNDW_LINKS
];
98 uint8_t PchHdaIDispLinkTmode
;
99 uint8_t PchHdaIDispLinkFrequency
;
100 uint8_t PchHdaIDispCodecDisconnect
;
102 /* PCIe Root Ports */
103 uint8_t PcieRpEnable
[CONFIG_MAX_ROOT_PORTS
];
104 /* PCIe output clocks type to PCIe devices.
105 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
107 uint8_t PcieClkSrcUsage
[CONFIG_MAX_PCIE_CLOCKS
];
108 /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
110 uint8_t PcieClkSrcClkReq
[CONFIG_MAX_PCIE_CLOCKS
];
112 /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
113 uint8_t PcieRpClkReqDetect
[CONFIG_MAX_ROOT_PORTS
];
115 /* PCIe RP L1 substate */
116 enum L1_substates_control
{
121 } PcieRpL1Substates
[CONFIG_MAX_ROOT_PORTS
];
127 uint8_t ScsEmmcHs400Enabled
;
129 /* Enable if SD Card Power Enable Signal is Active High */
130 uint8_t SdCardPowerEnableActiveHigh
;
132 /* Integrated Sensor */
133 uint8_t PchIshEnable
;
136 uint8_t Heci3Enabled
;
138 /* VR Config Settings for IA Core */
143 uint8_t IgdDvmt50PreAlloc
;
144 uint8_t SkipExtGfxScan
;
146 uint32_t GraphicsConfigPtr
;
148 /* HeciEnabled decides the state of Heci1 at end of boot
149 * Setting to 0 (default) disables Heci1 and hides the device from OS */
152 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
156 uint8_t enable_c6dram
;
158 * PRMRR size setting with below options
167 uint8_t PmTimerDisabled
;
169 * SerialIO device mode selection:
170 * PchSerialIoDisabled,
173 * PchSerialIoLegacyUart,
174 * PchSerialIoSkipInit
176 uint8_t SerialIoI2cMode
[CONFIG_SOC_INTEL_I2C_DEV_MAX
];
177 uint8_t SerialIoGSpiMode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
178 uint8_t SerialIoUartMode
[CONFIG_SOC_INTEL_UART_DEV_MAX
];
180 * GSPIn Default Chip Select Mode:
184 uint8_t SerialIoGSpiCsMode
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
186 * GSPIn Default Chip Select State:
190 uint8_t SerialIoGSpiCsState
[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
];
193 * TraceHubMode config
194 * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
196 uint8_t TraceHubMode
;
198 /* Debug interface selection */
200 DEBUG_INTERFACE_RAM
= (1 << 0),
201 DEBUG_INTERFACE_UART_8250IO
= (1 << 1),
202 DEBUG_INTERFACE_USB3
= (1 << 3),
203 DEBUG_INTERFACE_LPSS_SERIAL_IO
= (1 << 4),
204 DEBUG_INTERFACE_TRACEHUB
= (1 << 5),
205 } debug_interface_flag
;
207 /* GPIO SD card detect pin */
208 unsigned int sdcard_cd_gpio
;
210 /* Enable Pch iSCLK */
213 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
217 } CnviBtAudioOffload
;
224 * Override GPIO PM configuration:
225 * 0: Use FSP default GPIO PM program,
226 * 1: coreboot to override GPIO PM program
228 uint8_t gpio_override_pm
;
231 * GPIO PM configuration: 0 to disable, 1 to enable power gating
233 * Bit 5: MISCCFG_GPSIDEDPCGEN
234 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
235 * Bit 3: MISCCFG_GPRTCDLCGEN
236 * Bit 2: MISCCFG_GSXLCGEN
237 * Bit 1: MISCCFG_GPDPCGEN
238 * Bit 0: MISCCFG_GPDLCGEN
240 uint8_t gpio_pm
[TOTAL_GPIO_COMM
];
245 * 0:Disabled, 1:eDP, 2:MIPI DSI
247 uint8_t DdiPortAConfig
;
248 uint8_t DdiPortBConfig
;
250 /* Enable(1)/Disable(0) HPD */
259 /* Enable(1)/Disable(0) DDC */
268 /* Hybrid storage mode enable (1) / disable (0)
269 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
271 uint8_t HybridStorageMode
;
274 * Override CPU flex ratio value:
275 * CPU ratio value controls the maximum processor non-turbo ratio.
276 * Valid Range 0 to 63.
277 * In general descriptor provides option to set default cpu flex ratio.
278 * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
279 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
280 * Only override CPU flex ratio to not boot with non-turbo max.
282 uint8_t cpu_ratio_override
;
284 /* Skip CPU replacement check
287 * Setting this option to skip CPU replacement check to avoid the forced MRC training
288 * for the platforms with soldered down SOC.
290 uint8_t SkipCpuReplacementCheck
;
293 * SLP_S3 Minimum Assertion Width Policy
299 uint8_t PchPmSlpS3MinAssert
;
302 * SLP_S4 Minimum Assertion Width Policy
308 uint8_t PchPmSlpS4MinAssert
;
311 * SLP_SUS Minimum Assertion Width Policy
317 uint8_t PchPmSlpSusMinAssert
;
320 * SLP_A Minimum Assertion Width Policy
326 uint8_t PchPmSlpAMinAssert
;
329 * PCH PM Reset Power Cycle Duration
336 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
337 * stretch duration programmed in the following registers:
338 * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
339 * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
340 * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
341 * - PM_CFG.SLP_LAN_MIN_ASST_WDTH
343 uint8_t PchPmPwrCycDur
;
347 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
349 * Range varies based on XTAL clock:
350 * 0-1918 (Up to 191.8HMz) for 24MHz clock;
351 * 0-1535 (Up to 153.5MHz) for 19MHz clock.
353 uint16_t FivrRfiFrequency
;
356 * FIVR RFI Spread Spectrum
357 * Set the Spread Spectrum Range. <b>0: 0%</b>;
358 * FIVR RFI Spread Spectrum, in 0.1% increments.
359 * Range: 0.0% to 10.0% (0-100)
361 uint8_t FivrSpreadSpectrum
;
364 * Disable Fast Slew Rate for Deep Package C States for VR domains
365 * Disable Fast Slew Rate for Deep Package C States based on
366 * Acoustic Noise Mitigation feature enabled.
368 uint8_t FastPkgCRampDisable
;
371 * Slew Rate configuration for Deep Package C States for VR domains
372 * based on Acoustic Noise Mitigation feature enabled.
373 * 0: Fast/2 ; 1: Fast/4; 2: Fast/8; 3: Fast/16
375 uint8_t SlowSlewRate
;
378 * Enable or Disable Acoustic Noise Mitigation feature.
379 * 0: Disabled ; 1: Enabled
381 uint8_t AcousticNoiseMitigation
;
384 * Acoustic Noise Mitigation Range.Defines the maximum Pre-Wake
385 * randomization time in micro ticks.This can be programmed only
386 * if AcousticNoiseMitigation is enabled.
392 * Acoustic Noise Mitigation Range.Defines the maximum Ramp Up
393 * randomization time in micro ticks.This can be programmed only
394 * if AcousticNoiseMitigation is enabled.
400 * Acoustic Noise Mitigation Range.Defines the maximum Ramp Down
401 * randomization time in micro ticks.This can be programmed only
402 * if AcousticNoiseMitigation is enabled.
409 typedef struct soc_intel_jasperlake_config config_t
;