2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
61 You must build the coreboot crosscompiler for the board that you
64 To build all the GCC crosscompilers (takes a LONG time), run:
67 For help on individual architectures, run the command:
73 Use the GNU Compiler Collection (GCC) to build coreboot.
75 For details see http://gcc.gnu.org.
77 config COMPILER_LLVM_CLANG
78 bool "LLVM/clang (TESTING ONLY - Not currently working)"
80 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
124 Enable this option if you are working on the sconfig device tree
125 parser and made changes to sconfig.l or sconfig.y.
127 Otherwise, say N to use the provided pregenerated scanner/parser.
129 config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
132 depends on HAVE_OPTION_TABLE
134 Enable this option if coreboot shall read options from the "CMOS"
135 NVRAM instead of using hard-coded values.
137 config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
140 depends on USE_OPTION_TABLE
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
146 config UNCOMPRESSED_RAMSTAGE
150 config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
152 default y if !UNCOMPRESSED_RAMSTAGE
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
157 is connected through a slow link (i.e. SPI).
159 config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
170 config INCLUDE_CONFIG_FILE
171 bool "Include the coreboot .config file into the ROM image"
174 Include the .config file that was used to compile coreboot
175 in the (CBFS) ROM image. This is useful if you want to know which
176 options were used to build a specific coreboot.rom image.
178 Saying Y here will increase the image size by 2-3KB.
180 You can use the following command to easily list the options:
182 grep -a CONFIG_ coreboot.rom
184 Alternatively, you can also use cbfstool to print the image
185 contents (including the raw 'config' item we're looking for).
189 $ cbfstool coreboot.rom print
190 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
194 Name Offset Type Size
195 cmos_layout.bin 0x0 cmos layout 1159
196 fallback/romstage 0x4c0 stage 339756
197 fallback/ramstage 0x53440 stage 186664
198 fallback/payload 0x80dc0 payload 51526
199 config 0x8d740 raw 3324
200 (empty) 0x8e480 null 3610440
202 config NO_XIP_EARLY_STAGES
204 default n if ARCH_X86
207 Identify if early stages are eXecute-In-Place(XIP).
209 config EARLY_CBMEM_INIT
210 def_bool !LATE_CBMEM_INIT
212 config COLLECT_TIMESTAMPS
213 bool "Create a table of timestamps collected during boot"
216 Make coreboot create a table of timer-ID/timer-value pairs to
217 allow measuring time spent at different phases of the boot process.
220 bool "Allow use of binary-only repository"
223 This draws in the blobs repository, which contains binary files that
224 might be required for some chipsets or boards.
225 This flag ensures that a "Free" option remains available for users.
228 bool "Code coverage support"
229 depends on COMPILER_GCC
232 Add code coverage support for coreboot. This will store code
233 coverage information in CBMEM for extraction from user space.
236 config RELOCATABLE_MODULES
240 If RELOCATABLE_MODULES is selected then support is enabled for
241 building relocatable modules in the RAM stage. Those modules can be
242 loaded anywhere and all the relocations are handled automatically.
244 config RELOCATABLE_RAMSTAGE
245 depends on EARLY_CBMEM_INIT
246 bool "Build the ramstage to be relocatable in 32-bit address space."
248 select RELOCATABLE_MODULES
250 The reloctable ramstage support allows for the ramstage to be built
251 as a relocatable module. The stage loader can identify a place
252 out of the OS way so that copying memory is unnecessary during an S3
253 wake. When selecting this option the romstage is responsible for
254 determing a stack location to use for loading the ramstage.
256 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
257 depends on RELOCATABLE_RAMSTAGE
258 bool "Cache the relocated ramstage outside of cbmem."
261 The relocated ramstage is saved in an area specified by the
262 by the board and/or chipset.
264 config NO_STAGE_CACHE
268 Do not save any component in stage cache for resume path. On resume,
269 all components would be read back from CBFS again.
271 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
273 prompt "Bootblock behaviour"
274 default BOOTBLOCK_SIMPLE
276 config BOOTBLOCK_SIMPLE
277 bool "Always load fallback"
279 config BOOTBLOCK_NORMAL
280 bool "Switch to normal if CMOS says so"
284 # To be selected by arch, SoC or mainboard if it does not want use the normal
285 # src/lib/bootblock.c#main() C entry point.
286 config BOOTBLOCK_CUSTOM
290 config BOOTBLOCK_SOURCE
292 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
293 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
295 # To be selected by arch or platform if a C environment is available during the
296 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
297 config C_ENVIRONMENT_BOOTBLOCK
301 config SKIP_MAX_REBOOT_CNT_CLEAR
302 bool "Do not clear reboot count after successful boot"
304 depends on BOOTBLOCK_NORMAL
306 Do not clear the reboot count immediately after successful boot.
307 Set to allow the payload to control normal/fallback image recovery.
308 Note that it is the responsibility of the payload to reset the
309 normal boot bit to 1 after each successsful boot.
312 bool "Update existing coreboot.rom image"
315 If this option is enabled, no new coreboot.rom file
316 is created. Instead it is expected that there already
317 is a suitable file for further processing.
318 The bootblock will not be modified.
320 If unsure, select 'N'
322 config GENERIC_GPIO_LIB
326 If enabled, compile the generic GPIO library. A "generic" GPIO
327 implies configurability usually found on SoCs, particularly the
328 ability to control internal pull resistors.
334 Mainboards that can read a board ID from the hardware straps
335 (ie. GPIO) select this configuration option.
337 config BOARD_ID_MANUAL
340 depends on !BOARD_ID_AUTO
342 If you want to maintain a board ID, but the hardware does not
343 have straps to automatically determine the ID, you can say Y
344 here and add a file named 'board_id' to CBFS. If you don't know
345 what this is about, say N.
347 config BOARD_ID_STRING
350 depends on BOARD_ID_MANUAL
352 This string is placed in the 'board_id' CBFS file for indicating
355 config RAM_CODE_SUPPORT
359 If enabled, coreboot discovers RAM configuration (value obtained by
360 reading board straps) and stores it in coreboot table.
362 config BOOTSPLASH_IMAGE
363 bool "Add a bootsplash image"
365 Select this option if you have a bootsplash image that you would
366 like to add to your ROM.
368 This will only add the image to the ROM. To actually run it check
369 options under 'Display' section.
371 config BOOTSPLASH_FILE
372 string "Bootsplash path and filename"
373 depends on BOOTSPLASH_IMAGE
374 default "bootsplash.jpg"
376 The path and filename of the file to use as graphical bootsplash
377 screen. The file format has to be jpg.
383 source "src/mainboard/Kconfig"
385 # defaults for CBFS_SIZE are set at the end of the file.
387 hex "Size of CBFS filesystem in ROM"
389 This is the part of the ROM actually managed by CBFS, located at the
390 end of the ROM (passed through cbfstool -o) on x86 and at at the start
391 of the ROM (passed through cbfstool -s) everywhere else. It defaults
392 to span the whole ROM on all but Intel systems that use an Intel Firmware
393 Descriptor. It can be overridden to make coreboot live alongside other
394 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
398 string "fmap description file in fmd format"
399 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
402 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
403 but in some cases more complex setups are required.
404 When an fmd is specified, it overrides the default format.
406 config MAINBOARD_HAS_TPM2
410 There is a TPM device installed on the mainboard, and it is
411 compliant with version 2 TCG TPM specification. Could be connected
412 over LPC, SPI or I2C.
416 # load site-local kconfig to allow user specific defaults and overrides
417 source "site-local/Kconfig"
419 config SYSTEM_TYPE_LAPTOP
423 config CBFS_AUTOGEN_ATTRIBUTES
427 If this option is selected, every file in cbfs which has a constraint
428 regarding position or alignment will get an additional file attribute
429 which describes this constraint.
434 source "src/soc/*/*/Kconfig"
436 source "src/cpu/Kconfig"
437 comment "Northbridge"
438 source "src/northbridge/*/*/Kconfig"
439 comment "Southbridge"
440 source "src/southbridge/*/*/Kconfig"
442 source "src/superio/*/Kconfig"
443 comment "Embedded Controllers"
444 source "src/ec/acpi/Kconfig"
445 source "src/ec/*/*/Kconfig"
446 # FIXME move to vendorcode
447 source "src/drivers/intel/fsp1_0/Kconfig"
449 source "src/southbridge/intel/common/firmware/Kconfig"
450 source "src/vendorcode/*/Kconfig"
452 source "src/arch/*/Kconfig"
456 source "src/device/Kconfig"
458 menu "Generic Drivers"
459 source "src/drivers/*/Kconfig"
460 source "src/drivers/*/*/Kconfig"
463 source "src/acpi/Kconfig"
472 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
473 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
475 Enable this option to enable TPM support in coreboot.
481 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
482 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
484 Enable this option to enable TPM2 support in coreboot.
494 default 0x1000 if ARCH_X86
501 config MMCONF_SUPPORT_DEFAULT
505 config MMCONF_SUPPORT
509 config BOOTMODE_STRAPS
513 source "src/console/Kconfig"
515 config HAVE_ACPI_RESUME
519 config RESUME_PATH_SAME_AS_BOOT
521 default y if ARCH_X86
522 depends on HAVE_ACPI_RESUME
524 This option indicates that when a system resumes it takes the
525 same path as a regular boot. e.g. an x86 system runs from the
526 reset vector at 0xfffffff0 on both resume and warm/cold boot.
528 config HAVE_HARD_RESET
532 This variable specifies whether a given board has a hard_reset
533 function, no matter if it's provided by board code or chipset code.
535 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
539 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
543 This should be enabled on certain plaforms, such as the AMD
544 SR565x, that cannot handle concurrent CBFS accesses from
545 multiple APs during early startup.
547 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
551 config HAVE_MONOTONIC_TIMER
554 The board/chipset provides a monotonic timer.
556 config GENERIC_UDELAY
558 depends on HAVE_MONOTONIC_TIMER
560 The board/chipset uses a generic udelay function utilizing the
565 depends on HAVE_MONOTONIC_TIMER
567 Provide a timer queue for performing time-based callbacks.
569 config COOP_MULTITASKING
571 depends on TIMER_QUEUE && ARCH_X86
573 Cooperative multitasking allows callbacks to be multiplexed on the
574 main thread of ramstage. With this enabled it allows for multiple
575 execution paths to take place when they have udelay() calls within
581 depends on COOP_MULTITASKING
583 How many execution threads to cooperatively multitask with.
585 config HAVE_OPTION_TABLE
589 This variable specifies whether a given board has a cmos.layout
590 file containing NVRAM/CMOS bit definitions.
591 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
597 config HAVE_SMI_HANDLER
601 config PCI_IO_CFG_EXT
609 config CACHE_ROM_SIZE_OVERRIDE
613 # TODO: Can probably be removed once all chipsets have kconfig options for it.
618 config USE_WATCHDOG_ON_BOOT
626 Build board-specific VGA code.
632 Enable Unified Memory Architecture for graphics.
634 config HAVE_ACPI_TABLES
637 This variable specifies whether a given board has ACPI table support.
638 It is usually set in mainboard/*/Kconfig.
643 This variable specifies whether a given board has MP table support.
644 It is usually set in mainboard/*/Kconfig.
645 Whether or not the MP table is actually generated by coreboot
646 is configurable by the user via GENERATE_MP_TABLE.
648 config HAVE_PIRQ_TABLE
651 This variable specifies whether a given board has PIRQ table support.
652 It is usually set in mainboard/*/Kconfig.
653 Whether or not the PIRQ table is actually generated by coreboot
654 is configurable by the user via GENERATE_PIRQ_TABLE.
656 config MAX_PIRQ_LINKS
660 This variable specifies the number of PIRQ interrupt links which are
661 routable. On most chipsets, this is 4, INTA through INTD. Some
662 chipsets offer more than four links, commonly up to INTH. They may
663 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
664 table specifies links greater than 4, pirq_route_irqs will not
665 function properly, unless this variable is correctly set.
675 Build support for NHLT (non HD Audio) ACPI table generation.
677 #These Options are here to avoid "undefined" warnings.
678 #The actual selection and help texts are in the following menu.
682 config GENERATE_MP_TABLE
683 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
685 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
687 Generate an MP table (conforming to the Intel MultiProcessor
688 specification 1.4) for this board.
692 config GENERATE_PIRQ_TABLE
693 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
695 default HAVE_PIRQ_TABLE
697 Generate a PIRQ table for this board.
701 config GENERATE_SMBIOS_TABLES
703 bool "Generate SMBIOS tables"
706 Generate SMBIOS tables for this board.
710 config SMBIOS_PROVIDED_BY_MOBO
714 config MAINBOARD_SERIAL_NUMBER
715 string "SMBIOS Serial Number"
716 depends on GENERATE_SMBIOS_TABLES
717 depends on !SMBIOS_PROVIDED_BY_MOBO
720 The Serial Number to store in SMBIOS structures.
722 config MAINBOARD_VERSION
723 string "SMBIOS Version Number"
724 depends on GENERATE_SMBIOS_TABLES
725 depends on !SMBIOS_PROVIDED_BY_MOBO
728 The Version Number to store in SMBIOS structures.
730 config MAINBOARD_SMBIOS_MANUFACTURER
731 string "SMBIOS Manufacturer"
732 depends on GENERATE_SMBIOS_TABLES
733 depends on !SMBIOS_PROVIDED_BY_MOBO
734 default MAINBOARD_VENDOR
736 Override the default Manufacturer stored in SMBIOS structures.
738 config MAINBOARD_SMBIOS_PRODUCT_NAME
739 string "SMBIOS Product name"
740 depends on GENERATE_SMBIOS_TABLES
741 depends on !SMBIOS_PROVIDED_BY_MOBO
742 default MAINBOARD_PART_NUMBER
744 Override the default Product name stored in SMBIOS structures.
748 source "payloads/Kconfig"
752 # TODO: Better help text and detailed instructions.
754 bool "GDB debugging support"
756 depends on CONSOLE_SERIAL
758 If enabled, you will be able to set breakpoints for gdb debugging.
759 See src/arch/x86/lib/c_start.S for details.
762 bool "Wait for a GDB connection"
766 If enabled, coreboot will wait for a GDB connection.
769 bool "Halt when hitting a BUG() or assertion error"
772 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
775 bool "Output verbose CBFS debug messages"
778 This option enables additional CBFS related debug messages.
780 config HAVE_DEBUG_RAM_SETUP
783 config DEBUG_RAM_SETUP
784 bool "Output verbose RAM init debug messages"
786 depends on HAVE_DEBUG_RAM_SETUP
788 This option enables additional RAM init related debug messages.
789 It is recommended to enable this when debugging issues on your
790 board which might be RAM init related.
792 Note: This option will increase the size of the coreboot image.
796 config HAVE_DEBUG_CAR
801 depends on HAVE_DEBUG_CAR
803 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
804 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
805 # printk(BIOS_DEBUG, ...) calls.
807 bool "Output verbose Cache-as-RAM debug messages"
809 depends on HAVE_DEBUG_CAR
811 This option enables additional CAR related debug messages.
815 bool "Check PIRQ table consistency"
817 depends on GENERATE_PIRQ_TABLE
821 config HAVE_DEBUG_SMBUS
825 bool "Output verbose SMBus debug messages"
827 depends on HAVE_DEBUG_SMBUS
829 This option enables additional SMBus (and SPD) debug messages.
831 Note: This option will increase the size of the coreboot image.
836 bool "Output verbose SMI debug messages"
838 depends on HAVE_SMI_HANDLER
839 select SPI_FLASH_SMM if SPI_CONSOLE
841 This option enables additional SMI related debug messages.
843 Note: This option will increase the size of the coreboot image.
847 config DEBUG_SMM_RELOCATION
848 bool "Debug SMM relocation code"
850 depends on HAVE_SMI_HANDLER
852 This option enables additional SMM handler relocation related
855 Note: This option will increase the size of the coreboot image.
859 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
860 # printk(BIOS_DEBUG, ...) calls.
862 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
866 This option enables additional malloc related debug messages.
868 Note: This option will increase the size of the coreboot image.
872 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
873 # printk(BIOS_DEBUG, ...) calls.
875 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
879 This option enables additional ACPI related debug messages.
881 Note: This option will slightly increase the size of the coreboot image.
885 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
886 # printk(BIOS_DEBUG, ...) calls.
887 config REALMODE_DEBUG
888 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
891 depends on PCI_OPTION_ROM_RUN_REALMODE
893 This option enables additional x86emu related debug messages.
895 Note: This option will increase the time to emulate a ROM.
900 bool "Output verbose x86emu debug messages"
902 depends on PCI_OPTION_ROM_RUN_YABEL
904 This option enables additional x86emu related debug messages.
906 Note: This option will increase the size of the coreboot image.
910 config X86EMU_DEBUG_JMP
911 bool "Trace JMP/RETF"
913 depends on X86EMU_DEBUG
915 Print information about JMP and RETF opcodes from x86emu.
917 Note: This option will increase the size of the coreboot image.
921 config X86EMU_DEBUG_TRACE
922 bool "Trace all opcodes"
924 depends on X86EMU_DEBUG
926 Print _all_ opcodes that are executed by x86emu.
928 WARNING: This will produce a LOT of output and take a long time.
930 Note: This option will increase the size of the coreboot image.
934 config X86EMU_DEBUG_PNP
935 bool "Log Plug&Play accesses"
937 depends on X86EMU_DEBUG
939 Print Plug And Play accesses made by option ROMs.
941 Note: This option will increase the size of the coreboot image.
945 config X86EMU_DEBUG_DISK
948 depends on X86EMU_DEBUG
950 Print Disk I/O related messages.
952 Note: This option will increase the size of the coreboot image.
956 config X86EMU_DEBUG_PMM
959 depends on X86EMU_DEBUG
961 Print messages related to POST Memory Manager (PMM).
963 Note: This option will increase the size of the coreboot image.
968 config X86EMU_DEBUG_VBE
969 bool "Debug VESA BIOS Extensions"
971 depends on X86EMU_DEBUG
973 Print messages related to VESA BIOS Extension (VBE) functions.
975 Note: This option will increase the size of the coreboot image.
979 config X86EMU_DEBUG_INT10
980 bool "Redirect INT10 output to console"
982 depends on X86EMU_DEBUG
984 Let INT10 (i.e. character output) calls print messages to debug output.
986 Note: This option will increase the size of the coreboot image.
990 config X86EMU_DEBUG_INTERRUPTS
991 bool "Log intXX calls"
993 depends on X86EMU_DEBUG
995 Print messages related to interrupt handling.
997 Note: This option will increase the size of the coreboot image.
1001 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1002 bool "Log special memory accesses"
1004 depends on X86EMU_DEBUG
1006 Print messages related to accesses to certain areas of the virtual
1007 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1009 Note: This option will increase the size of the coreboot image.
1013 config X86EMU_DEBUG_MEM
1014 bool "Log all memory accesses"
1016 depends on X86EMU_DEBUG
1018 Print memory accesses made by option ROM.
1019 Note: This also includes accesses to fetch instructions.
1021 Note: This option will increase the size of the coreboot image.
1025 config X86EMU_DEBUG_IO
1026 bool "Log IO accesses"
1028 depends on X86EMU_DEBUG
1030 Print I/O accesses made by option ROM.
1032 Note: This option will increase the size of the coreboot image.
1036 config X86EMU_DEBUG_TIMINGS
1037 bool "Output timing information"
1039 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1041 Print timing information needed by i915tool.
1046 bool "Output verbose TPM debug messages"
1048 depends on TPM || TPM2
1050 This option enables additional TPM related debug messages.
1052 config DEBUG_SPI_FLASH
1053 bool "Output verbose SPI flash debug messages"
1055 depends on SPI_FLASH
1057 This option enables additional SPI flash related debug messages.
1059 config DEBUG_USBDEBUG
1060 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1064 This option enables additional USB 2.0 debug dongle related messages.
1066 Select this to debug the connection of usbdebug dongle. Note that
1067 you need some other working console to receive the messages.
1069 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1070 # Only visible with the right southbridge and loglevel.
1071 config DEBUG_INTEL_ME
1072 bool "Verbose logging for Intel Management Engine"
1075 Enable verbose logging for Intel Management Engine driver that
1076 is present on Intel 6-series chipsets.
1080 bool "Trace function calls"
1083 If enabled, every function will print information to console once
1084 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1085 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1086 of calling function. Please note some printk related functions
1087 are omitted from trace to have good looking console dumps.
1089 config DEBUG_COVERAGE
1090 bool "Debug code coverage"
1094 If enabled, the code coverage hooks in coreboot will output some
1095 information about the coverage data that is dumped.
1099 # These probably belong somewhere else, but they are needed somewhere.
1100 config ENABLE_APIC_EXT_ID
1104 config WARNINGS_ARE_ERRORS
1108 # TODO: Remove this when all platforms are fixed.
1109 config IASL_WARNINGS_ARE_ERRORS
1112 Select to Fail the build if a IASL generates a warning.
1113 This will be defaulted to disabled for the platforms that
1114 currently fail. This allows the REST of the platforms to
1115 have this check enabled while we're working to get those
1118 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1121 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1122 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1123 # mutually exclusive. One of these options must be selected in the
1124 # mainboard Kconfig if the chipset supports enabling and disabling of
1125 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1126 # in mainboard/Kconfig to know if the button should be enabled or not.
1128 config POWER_BUTTON_DEFAULT_ENABLE
1131 Select when the board has a power button which can optionally be
1132 disabled by the user.
1134 config POWER_BUTTON_DEFAULT_DISABLE
1137 Select when the board has a power button which can optionally be
1138 enabled by the user, e.g. when the board ships with a jumper over
1139 the power switch contacts.
1141 config POWER_BUTTON_FORCE_ENABLE
1144 Select when the board requires that the power button is always
1147 config POWER_BUTTON_FORCE_DISABLE
1150 Select when the board requires that the power button is always
1151 disabled, e.g. when it has been hardwired to ground.
1153 config POWER_BUTTON_IS_OPTIONAL
1155 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1156 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1158 Internal option that controls ENABLE_POWER_BUTTON visibility.
1164 Internal option that controls whether we compile in register scripts.
1166 config MAX_REBOOT_CNT
1170 Internal option that sets the maximum number of bootblock executions allowed
1171 with the normal image enabled before assuming the normal image is defective
1172 and switching to the fallback image.
1178 This is the part of the ROM actually managed by CBFS. Set it to be
1179 equal to the full rom size if that hasn't been overridden by the
1180 chipset or mainboard.
1182 config DEBUG_BOOT_STATE
1186 Control debugging of the boot state machine. When selected displays
1187 the state boundaries in ramstage.
1189 config CREATE_BOARD_CHECKLIST
1193 When selected, creates a webpage showing the implementation status for
1194 the board. Routines highlighted in green are complete, yellow are
1195 optional and red are required and must be implemented. A table is
1196 produced for each stage of the boot process except the bootblock. The
1197 red items may be used as an implementation checklist for the board.
1199 config MAKE_CHECKLIST_PUBLIC
1203 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1204 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1207 config CHECKLIST_DATA_FILE_LOCATION
1210 Location of the <stage>_complete.dat and <stage>_optional.dat files
1211 that are consumed during checklist processing. <stage>_complete.dat
1212 contains the symbols that are expected to be in the resulting image.
1213 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1214 a list of weak symbols which the resulting image may consume. Other
1215 symbols contained only in <stage>_complete.dat will be flagged as
1216 required and not implemented if a weak implementation is found in the